Volume 12,
Number 1,
January 2007
- Anup Gangwar, M. Balakrishnan, Anshul Kumar:
Impact of intercluster communication mechanisms on ILP in clustered VLIW architectures.
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- Nicholas H. Zamora, Xiaoping Hu, Radu Marculescu:
System-level performance/power analysis for platform-based design of multimedia applications.
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- Chiu-Wing Sham, Evangeline F. Y. Young:
Area reduction by deadspace utilization on interconnect optimized floorplan.
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- Lei Li, Zhanglei Wang, Krishnendu Chakrabarty:
Scan-BIST based on cluster analysis and the encoding of repeating sequences.
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- Yuan Cai, Marcus T. Schmitz, Bashir M. Al-Hashimi, Sudhakar M. Reddy:
Workload-ahead-driven online energy minimization techniques for battery-powered embedded systems with time-constraints.
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- Xinping Zhu, Sharad Malik:
A hierarchical modeling framework for on-chip communication architectures of multiprocessing SoCs.
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- Subhashis Majumder, Susmita Sur-Kolay, Bhargab B. Bhattacharya, Swarup Kumar Das:
Hierarchical partitioning of VLSI floorplans by staircases.
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- Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt:
Instruction set synthesis with efficient instruction encoding for configurable processors.
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Volume 12,
Number 2,
April 2007
- Nikil Dutt:
Editorial.
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- Chao Wang, Zijiang Yang, Franjo Ivancic, Aarti Gupta:
Disjunctive image computation for software verification.
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- Bren Mochocki, Xiaobo Sharon Hu, Gang Quan:
Transition-overhead-aware voltage scheduling for fixed-priority real-time systems.
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- Hongliang Chang, Sachin S. Sapatnekar:
Prediction of leakage power under process uncertainties.
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- Sumit Mohanty, Viktor K. Prasanna:
A model-based extensible framework for efficient application design using FPGA.
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- Weiyu Tang, Arun Kejariwal, Alexander V. Veidenbaum, Alexandru Nicolau:
A predictive decode filter cache for reducing power consumption in embedded processors.
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- Ilya Issenin, Erik Brockmeyer, Miguel Miranda, Nikil Dutt:
DRDU: A data reuse analysis technique for efficient scratch-pad memory management.
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- Mohammad Hosseinabady, Pejman Lotfi-Kamran, Zainalabedin Navabi:
Low test application time resource binding for behavioral synthesis.
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- Mohammed ElShoukry, Mohammad Tehranipoor, C. P. Ravikumar:
A critical-path-aware partial gating approach for test power reduction.
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- Irith Pomeranz, Sudhakar M. Reddy:
Forming N-detection test sets without test generation.
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- Hongbing Fan, Jiping Liu, Yu-Liang Wu, Chak-Chung Cheung:
The exact channel density and compound design for generic universal switch blocks.
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Volume 12,
Number 3,
August 2007
- Sung Kyu Lim, Massoud Pedram:
Introduction to special issue on demonstrable software systems and hardware platforms.
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- Chia-Jui Hsu, Ming-Yung Ko, Shuvra S. Bhattacharyya, Suren Ramasubbu, José Luis Pino:
Efficient simulation of critical synchronous dataflow graphs.
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- Fernando Herrera, Eugenio Villar:
A framework for heterogeneous specification and design of electronic embedded systems in SystemC.
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- Hyung Gyu Lee, Naehyuck Chang, Ümit Y. Ogras, Radu Marculescu:
On-chip communication architecture exploration: A quantitative evaluation of point-to-point, bus, and network-on-chip approaches.
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- Soonhoi Ha, Sungchan Kim, Choonseung Lee, Youngmin Yi, Seongnam Kwon, Young-Pyo Joo:
PeaCE: A hardware-software codesign environment for multimedia embedded systems.
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- David Atienza, Pablo Garcia Del Valle, Giacomo Paci, Francesco Poletti, Luca Benini, Giovanni De Micheli, Jose Manuel Mendias, Román Hermida:
HW-SW emulation framework for temperature-aware design in MPSoCs.
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- Wei Wu, Lingling Jin, Jun Yang, Pu Liu, Sheldon X.-D. Tan:
Efficient power modeling and software thermal sensing for runtime temperature monitoring.
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- Po-Kuan Huang, Soheil Ghiasi:
Efficient and scalable compiler-directed energy optimization for realtime applications.
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- Yiyu Shi, Paul Mesa, Hao Yu, Lei He:
Circuit-simulated obstacle-aware Steiner routing.
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- Lakshmi N. Chakrapani, Pinar Korkmaz, Bilge E. S. Akgul, Krishna V. Palem:
Probabilistic system-on-a-chip architectures.
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- Ang-Chih Hsieh, Tzu-Teng Lin, Tsuang-Wei Chang, TingTing Hwang:
A functionality-directed clustering technique for low-power MTCMOS design - computation of simultaneously discharging current.
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- Tathagato Rai Dastidar, P. P. Chakrabarti:
A verification system for transient response of analog circuits.
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- Kai-Hui Chang, Igor L. Markov, Valeria Bertacco:
Postplacement rewiring by exhaustive search for functional symmetries.
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- Deepak Mathaikutty, Hiren D. Patel, Sandeep K. Shukla, Axel Jantsch:
EWD: A metamodeling driven customizable multi-MoC system modeling framework.
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- Greg Stitt, Frank Vahid:
Binary synthesis.
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- Michalis D. Galanis, Gregory Dimitroulakos, Spyros Tragoudas, Costas E. Goutis:
Speedups in embedded systems with a high-performance coprocessor datapath.
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- Suchismita Roy, P. P. Chakrabarti, Pallab Dasgupta:
Event propagation for accurate circuit delay calculation using SAT.
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Volume 12,
Number 4,
September 2007
- Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang:
Temporal floorplanning using the three-dimensional transitive closure subGraph.
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- Jinfeng Liu, Pai H. Chou:
Idle energy minimization by mode sequence optimization.
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- Bita Gorjiara, Nader Bagherzadeh, Pai H. Chou:
Ultra-fast and efficient algorithm for energy optimization by gradient-based stochastic voltage and task scheduling.
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- Peter Vanbroekhoven, Gerda Janssens, Maurice Bruynooghe, Francky Catthoor:
A practical dynamic single assignment transformation.
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- Yuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Masaharu Imai:
Methodology for operation shuffling and L0 cluster generation for low energy heterogeneous VLIW processors.
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- Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller:
Techniques for the synthesis of reversible Toffoli networks.
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- Youcef Bouchebaba, Bruno Girodias, Gabriela Nicolescu, El Mostapha Aboulhamid, Bruno Lavigueur, Pierre G. Paulin:
MPSoC memory optimization using program transformation.
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- Dipankar Das, P. P. Chakrabarti, Rajeev Kumar:
Functional verification of task partitioning for multiprocessor embedded systems.
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- Shih-Hsu Huang, Yow-Tyng Nieh:
Clock skew scheduling with race conditions considered.
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- Gang Wang, Wenrui Gong, Brian DeRenzi, Ryan Kastner:
Exploring time/resource trade-offs by solving dual scheduling problems with the ant colony optimization.
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- Swaroop Ghosh, Swarup Bhunia, Kaushik Roy:
Low-Power and testable circuit synthesis using Shannon decomposition.
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- Christopher Ostler, Karam S. Chatha, Vijay Ramamurthi, Krishnan Srinivasan:
ILP and heuristic techniques for system-level design on network processor architectures.
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- Sivaram Gopalakrishnan, Priyank Kalla:
Optimization of polynomial datapaths using finite ring algebra.
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- Qubo Hu, Per Gunnar Kjeldsberg, Arnout Vandecappelle, Martin Palkovic, Francky Catthoor:
Incremental hierarchical memory size estimation for steering of loop transformations.
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- Yi-Ping You, Chung-Wen Huang, Jenq Kuen Lee:
Compilation for compact power-gating controls.
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- Gang Chen, Xiaoyu Song, Feng Liu, QingPing Tan, Fei He:
A note on "a mapping algorithm for computer-assisted exploration in the design of embedded systems".
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Copyright © Sun May 17 00:29:44 2009
by Michael Ley (ley@uni-trier.de)