2008 |
23 | EE | Hideyuki Ichihara,
Tomoyuki Saiki,
Tomoo Inoue:
An Architecture of Embedded Decompressor with Reconfigurability for Test Compression.
IEICE Transactions 91-D(3): 713-719 (2008) |
22 | EE | Tomoo Inoue,
Takashi Fujii,
Hideyuki Ichihara:
A Self-Test of Dynamically Reconfigurable Processors with Test Frames.
IEICE Transactions 91-D(3): 756-762 (2008) |
2007 |
21 | EE | Tomoo Inoue,
Takashi Fujii,
Hideyuki Ichihara:
Optimal Contexts for the Self-Test of Coarse Grain Dynamically Reconfigurable Processors.
European Test Symposium 2007: 117-124 |
20 | EE | Tomokazu Yoneda,
Akiko Shuto,
Hideyuki Ichihara,
Tomoo Inoue,
Hideo Fujiwara:
TAM Design and Optimization for Transparency-Based SoC Test.
VTS 2007: 381-388 |
19 | EE | Hideyuki Ichihara,
Toshihiro Ohara,
Michihiro Shintani,
Tomoo Inoue:
A Variable-Length Coding Adjustable for Compressed Test Application.
IEICE Transactions 90-D(8): 1235-1242 (2007) |
18 | EE | Hideyuki Ichihara,
Toshimasa Kuchii,
Masaaki Yamadate,
Hideaki Sakaguchi,
Hiroshi Uemura,
Kozo Kinoshita:
A statistical error model for image sensors and its testing.
Systems and Computers in Japan 38(11): 1-11 (2007) |
2006 |
17 | EE | Tomoyuki Saiki,
Hideyuki Ichihara,
Tomoo Inoue:
A Reconfigurable Embedded Decompressor for Test Compression.
DELTA 2006: 301-308 |
2005 |
16 | EE | Michihiro Shintani,
Toshihiro Ohara,
Hideyuki Ichihara,
Tomoo Inoue:
A Huffman-based coding with efficient test application.
ASP-DAC 2005: 75-78 |
15 | EE | Hideyuki Ichihara,
Tomoo Inoue,
Naoki Okamoto,
Toshinori Hosokawa,
Hideo Fujiwara:
An Effective Design for Hierarchical Test Generation Based on Strong Testability.
Asian Test Symposium 2005: 288-293 |
14 | EE | Hideyuki Ichihara,
Michihiro Shintani,
Tomoo Inoue:
Huffman-Based Test Response Coding.
IEICE Transactions 88-D(1): 158-161 (2005) |
13 | EE | Yoshinobu Higami,
Seiji Kajihara,
Hideyuki Ichihara,
Yuzo Takamatsu:
Test cost reduction for logic circuits: Reduction of test data volume and test application time.
Systems and Computers in Japan 36(6): 69-83 (2005) |
2004 |
12 | EE | Hideyuki Ichihara,
Masakuni Ochi,
Michihiro Shintani,
Tomoo Inoue:
A Test Decompression Scheme for Variable-Length Coding.
Asian Test Symposium 2004: 426-431 |
2003 |
11 | EE | Hideyuki Ichihara,
Michihiro Shintani,
Toshihiro Ohara,
Tomoo Inoue:
Test Response Compression Based on Huffman Coding.
Asian Test Symposium 2003: 446-451 |
10 | EE | Hideyuki Ichihara,
Tomoo Inoue:
Test Generation for Acyclic Sequential Circuits with Single Stuck-at Fault Combinational ATPG.
DATE 2003: 11180-11181 |
9 | EE | Hideyuki Ichihara,
Kozo Kinoshita,
Koji Isodono,
Shigeki Nishikawa:
Channel Width Test Data Compression under a Limited Number of Test Inputs and Outputs.
VLSI Design 2003: 329-334 |
2002 |
8 | EE | Hideyuki Ichihara,
Tomoo Inoue:
Generating Small Test Sets for Test Compression/Decompression Scheme Using Statistical Coding.
DELTA 2002: 396-402 |
2001 |
7 | EE | Hideyuki Ichihara,
Atsuhiro Ogawa,
Tomoo Inoue,
Akio Tamura:
Dynamic Test Compression Using Statistical Coding.
Asian Test Symposium 2001: 143- |
2000 |
6 | EE | Hideyuki Ichihara,
Kozo Kinoshita,
Irith Pomeranz,
Sudhakar M. Reddy:
Test Transformation to Improve Compaction by Statistical Encoding.
VLSI Design 2000: 294-299 |
1999 |
5 | EE | Hideyuki Ichihara,
Kozo Kinoshita,
Seiji Kajihara:
On an Effective Selection of IDDQ Measurement Vectors for Sequential Circuits.
Asian Test Symposium 1999: 147-152 |
4 | EE | Hideyuki Ichihara,
Kozo Kinoshita,
Seiji Kajihara:
On Test Generation with A Limited Number of Tests.
Great Lakes Symposium on VLSI 1999: 12-15 |
1998 |
3 | EE | Hideyuki Ichihara,
Seiji Kajihara,
Kozo Kinoshita:
An Efficient Procedure for Obtaining Implication Relations and Its Application to Redundancy Identification.
Asian Test Symposium 1998: 58-63 |
1997 |
2 | EE | Hideyuki Ichihara,
Kozo Kinoshita:
On Acceleration of Logic Circuits Optimization Using Implication Relations.
Asian Test Symposium 1997: 222-227 |
1 | EE | Hideyuki Ichihara,
Kozo Kinoshita,
Seiji Kajihara:
On invariant implication relations for removing partial circuits.
Systems and Computers in Japan 28(7): 39-47 (1997) |