ICCD 2002:
Freiburg,
Germany
20th International Conference on Computer Design (ICCD 2002), VLSI in Computers and Processors, 16-18 September 2002, Freiburg, Germany, Proceedings.
IEEE Computer Society 2002, ISBN 0-7695-1700-5 BibTeX
@proceedings{DBLP:conf/iccd/2002,
title = {20th International Conference on Computer Design (ICCD 2002),
VLSI in Computers and Processors, 16-18 September 2002, Freiburg,
Germany, Proceedings},
booktitle = {ICCD},
publisher = {IEEE Computer Society},
year = {2002},
isbn = {0-7695-1700-5},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Keynote Addresses
Computers in Media,
Mobile and Servers
Physical Design
- Chung-Seok (Andy) Seo, Abhijit Chatterjee:
A CAD Tool for System-on-Chip Placement and Routing with Free-Space Optical Interconnect.
24-29
Electronic Edition (link) BibTeX
- Hongyu Chen, Bo Yao, Feng Zhou, Chung-Kuan Cheng:
Physical Planning Of On-Chip Interconnect Architectures.
30-35
Electronic Edition (link) BibTeX
- Stan Y. Liao, Narendra V. Shenoy, William Nicholls:
An Efficient External-Memory Implementation of Region Query with Application to Area Routing.
36-41
Electronic Edition (link) BibTeX
- Chang-Tzu Lin, De-Sheng Chen, Yi-Wen Wang:
GPE: A New Representation for VLSI Floorplan Problem.
42-44
Electronic Edition (link) BibTeX
- Xiaojian Yang, Bo-Kyung Choi, Majid Sarrafzadeh:
A Standard-Cell Placement Tool for Designs with High Row Utilization.
45-
Electronic Edition (link) BibTeX
Verification
Design ITRS 2001 - Issues and Solutions
Data Path Elements for Multi-GHz Design
- Sumio Morioka, Akashi Satoh:
A 10 Gbps Full-AES Crypto Design with a Twisted-BDD S-Box Architecture.
98-103
Electronic Edition (link) BibTeX
- Alexander Taubin, Karl Fant, John McCardle:
Design of Delay-Insensitive Three Dimension Pipeline Array Multiplier for Image Processing.
104-111
Electronic Edition (link) BibTeX
- Eduardo A. C. da Costa, Sergio Bampi, José Monteiro:
A New Architecture for Signed Radix-2m Pure Array Multipliers.
112-117
Electronic Edition (link) BibTeX
- Oguz Ergin, Kanad Ghose, Gurhan Kucuk, Dmitry Ponomarev:
A Circuit-Level Implementation of Fast, Energy-Efficient CMOS Comparators for High-Performance Microprocessors.
118-121
Electronic Edition (link) BibTeX
- Tyler Thorp, Dean Liu:
Analysis of Blocking Dynamic Circuits.
122-
Electronic Edition (link) BibTeX
Multimedia and and Arithmetic
Methodology Issues for High Performance Designs
- Louis Scheffer:
Methodologies and Tools for Pipelined On-Chip Interconnect.
152-157
Electronic Edition (link) BibTeX
- Rita Yu Chen, Paul Yip, Georgios Konstadinidis, Andrew Demas, Fabian Klass, Rob Mains, Margaret Schmitt, Dina Bistry:
Timing Window Applications in UltraSPARC-IIIi? Microprocessor Design.
158-163
Electronic Edition (link) BibTeX
- B. Chappell, X. Wang, P. Patra, Prashant Saxena, J. Vendrell, Satyanarayan Gupta, S. Varadarajan, W. Gomes, S. Hussain, H. Krishnamurthy, M. Venkateshmurthy, S. Jain:
A System-Level Solution to Domino Synthesis with 2 GHz Application.
164-
Electronic Edition (link) BibTeX
Low-Power Microarchitecture
Design for Testability
Sensor Networks:
New Architecture and Synthesis Challenges
Computer Systems Design and Applications I
Analog Test and Dependability
The Imagine Processor
- Ujval J. Kapasi, William J. Dally, Scott Rixner, John D. Owens, Brucek Khailany:
The Imagine Stream Processor.
282-288
Electronic Edition (link) BibTeX
- Brucek Khailany, William J. Dally, Andrew Chang, Ujval J. Kapasi, Jinyung Namkoong, Brian Towles:
VLSI Design and Verification of the Imagine Processor.
289-294
Electronic Edition (link) BibTeX
- John D. Owens, Scott Rixner, Ujval J. Kapasi, Peter R. Mattson, Brian Towles, Ben Serebrin, William J. Dally:
Media Processing Applications on the Imagine Stream Processor.
295-302
Electronic Edition (link) BibTeX
- Ben Serebrin, John D. Owens, Chen H. Chen, Stephen P. Crago, Ujval J. Kapasi, Peter R. Mattson, Jinyung Namkoong, Scott Rixner, William J. Dally:
A Stream Processor Development Platform.
303-
Electronic Edition (link) BibTeX
Low Power Circuit Techniques
Cache Memories
- Yen-Jen Chang, Feipei Lai, Shanq-Jang Ruan:
Cache Design for Eliminating the Address Translation Bottleneck and Reducing the Tag Area Cost.
334-339
Electronic Edition (link) BibTeX
- Jinwoo Kim, Krishna V. Palem, Weng-Fai Wong:
A Framework for Data Prefetching Using Off-Line Training of Markovian Predictors.
340-347
Electronic Edition (link) BibTeX
- Afzal Hossain, Daniel J. Pease, James S. Burns, Nasima Parveen:
Trace Cache Performance Parameters.
348-355
Electronic Edition (link) BibTeX
- Terry Lyon, Eric Delano, Cameron McNairy, Dean Mulla:
Data Cache Design Considerations for the Itanium® 2 Processor.
356-
Electronic Edition (link) BibTeX
Processors in Automotive Systems
- Joachim Schlosser:
Requirements for Automotive System Engineering Tools.
364-369
Electronic Edition (link) BibTeX
- Paolo Giusto, Jean-Yves Brunel, Alberto Ferrari, Eliane Fourgeau, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli:
Automotive Virtual Integration Platforms: Why's, What's, and How's.
370-378
Electronic Edition (link) BibTeX
- Paolo Giusto, Jean-Yves Brunel, Alberto Ferrari, Eliane Fourgeau, Luciano Lavagno, Barry O'Rourke, Alberto L. Sangiovanni-Vincentelli, Emanuele Guasto:
Models of IP's for Automotive Virtual Integration Platforms.
379-
Electronic Edition (link) BibTeX
Power Management and High Level Synthesis
Speculative and Packet Oriented Architectures
Interconnect Modeling and Analysis
Issues in Processor Architecture
- Zhigang Hu, Philo Juang, Kevin Skadron, Douglas W. Clark, Margaret Martonosi:
Applying Decay Strategies to Branch Predictors for Leakage Energy Savings.
442-445
Electronic Edition (link) BibTeX
- Ann Gordon-Ross, Frank Vahid:
Dynamic Loop Caching Meets Preloaded Loop Caching - A Hybrid Approach.
446-449
Electronic Edition (link) BibTeX
- Manfred Ley, Herbert Grünbacher:
TTA-C2, A Single Chip Communication Controller for the Time-Triggered-Protocol.
450-453
Electronic Edition (link) BibTeX
- Aristides Efthymiou, Jim D. Garside:
Adaptive Pipeline Depth Control for Processor Power-Management.
454-457
Electronic Edition (link) BibTeX
- Amirali Baniasadi, Andreas Moshovos:
Branch Predictor Prediction: A Power-Aware Branch Predictor for High-Performance Processors.
458-461
Electronic Edition (link) BibTeX
- Joshua J. Yi, David J. Lilja:
Improving Processor Performance by Simplifying and Bypassing Trivial Computations.
462-
Electronic Edition (link) BibTeX
Low Power Test,
Diagnosis
System Design Issues
Computer Systems Design and Applications II
Copyright © Sat May 16 23:16:37 2009
by Michael Ley (ley@uni-trier.de)
