13th Asian Test Symposium (ATS 2004), 15-17 November 2004, Kenting, Taiwan.
IEEE Computer Society 2004, ISBN 0-7695-2235-1 BibTeX
Session A1:
SOC Testing
Session B1:
Low-Power Testing
- Kuen-Jong Lee, Shaing-Jer Hsu, Chia-Ming Ho:
Test Power Reduction with Multiple Capture Orders.
26-31
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- Zhiqiang You, Ken-ichi Yamaguchi, Michiko Inoue, Jacob Savir, Hideo Fujiwara:
Power-Constrained DFT Algorithms for Non-Scan BIST-able RTL Data Paths.
32-39
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- Nan-Cheng Lai, Sying-Jyan Wang, Yu-Hsuan Fu:
Low Power BIST with Smoother and Scan-Chain Reorder .
40-45
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- Yoshinobu Higami, Seiji Kajihara, Shin-ya Kobayashi, Yuzo Takamatsu:
Techniques for Finding Xs in Test Sequences for Sequential Circuits and Applications to Test Length/Power Reduction.
46-49
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Session C1:
Analog BIST
Session A2:
Advanced DFT
Session B2:
Fault Analysis
- John P. Hayes, Ilia Polian, Bernd Becker:
Testing for Missing-Gate Faults in Reversible Circuits.
100-105
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- Irith Pomeranz, Sudhakar M. Reddy:
Properties of Maximally Dominating Faults.
106-111
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- Masaki Hashizume, Daisuke Yoneda, Hiroyuki Yotsuyanagi, Tetsuo Tada, Takeshi Koyama, Ikuro Morita, Takeomi Tamesada:
I_DDQ Test Method Based on Wavelet Transformation for Noisy Current Measurement Environment.
112-117
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- Klaus Rothbart, Ulrich Neffe, Christian Steger, Reinhold Weiss, Edgar Rieger, Andreas Mühlberger:
High Level Fault Injection for Attack Simulation in Smart Cards.
118-121
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Session C2:
Cross-Talk Testing
Session A3:
Functional Testing
Session B3:
Logic BIST
- Chaowen Yu, Sudhakar M. Reddy, Irith Pomeranz:
Weighted Pseudo-Random BIST for N-Detection of Single Stuck-at Faults.
178-183
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- Santosh Biswas, Siddhartha Mukhopadhyay, Amit Patra:
A BIST Approach to On-Line Monitoring of Digital VLSI Circuits: A CAD Tool.
184-189
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- Masayuki Arai, Harunobu Kurokawa, Kenichi Ichino, Satoshi Fukumoto, Kazuhiko Iwasaki:
Seed Selection Procedure for LFSR-Based BIST with Multiple Scan Chains and Phase Shifters.
190-195
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- Sukanta Das, Anirban Kundu, Biplab K. Sikdar:
Nonlinear CA Based Design of Test Set Generator Targeting Pseudo-Random Pattern Resistant Faults.
196-201
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Session C3:
Fault Diagnosis
- Wu-Tung Cheng, Kun-Han Tsai, Yu Huang, Nagesh Tamarapalli, Janusz Rajski:
Compactor Independent Direct Diagnosis.
204-209
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- S. Ghosh, K. W. Lai, Wen-Ben Jone, Shih-Chieh Chang:
Scan Chain Fault Identification Using Weight-Based Codes for SoC Circuits.
210-215
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- Hiroshi Takahashi, Yukihiro Yamamoto, Yoshinobu Higami, Yuzo Takamatsu:
Enhancing BIST Based Single/Multiple Stuck-at Fault Diagnosis by Ambiguous Test Set.
216-221
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- Yuichi Sato, Hiroshi Takahashi, Yoshinobu Higami, Yuzo Takamatsu:
Failure Analysis of Open Faults by Using Detecting/Un-detecting Information on Tests.
222-227
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Session A4:
SOC Test Scheduling
- Zhiyuan He, Gert Jervan, Zebo Peng, Petru Eles:
Hybrid BIST Test Scheduling Based on Defect Probabilities.
230-235
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- Yu Hu, Yinhe Han, Huawei Li, Tao Lv, Xiaowei Li:
Pair Balance-Based Test Scheduling for SOCs.
236-241
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- Jung-Been Im, Sunghoon Chun, Geunbae Kim, Jin-Ho Ahn, Sungho Kang:
RAIN (RAndom Insertion) Scheduling Algorithm for SoC Test.
242-247
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- Wei-Lun Wang:
March Based Memory Core Test Scheduling for SOC.
248-253
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- Stina Edbom, Erik Larsson:
An Integrated Technique for Test Vector Selection and Test Scheduling under Test Time Constraint.
254-257
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Session B4:
Memory Testing
- Chih-Tsun Huang, Jen-Chieh Yeh, Yuan-Yuan Shih, Rei-Fu Huang, Cheng-Wen Wu:
On Test and Diagnostics of Flash Memories.
260-265
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- Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Bastian Hage-Hassan:
Resistive-Open Defects in Embedded-SRAM Core Cells: Analysis and March Test Solution.
266-271
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- Yi-Ming Sheng, Ming-Jun Hsiao, Tsin-Yuan Chang:
A Measurement Unit for Input Signal Analysis of SRAM Sense Amplifier.
272-276
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- Jin-Fu Li, Chao-Da Huang:
An Efficient Diagnosis Scheme for Random Access Memories.
277-282
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- Said Hamdioui, John Delos Reyes, Zaid Al-Ars:
Evaluation of Intra-Word Faults in Word-Oriented RAMs.
283-288
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Session C4:
Analog Testing
Session A5:
Testable Design
Session B5:
Testability Analysis
Session C5:
Yield and Reliability
Session A6:
Fault Tolerance
Session B6:
FPGA Testing and Test Reduction
- Shyue-Kung Lu, Hung-Chin Wu, Shoei-Jia Yan, Yu-Cheng Tsai:
Testing and Diagnosis Techniques for LUT-Based FPGA's.
414-419
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- Donghoon Han, Abhijit Chatterjee:
Device Resizing Based Optimization of Analog Circuits for Reduced Test Cost: Cost Metric and Case Study.
420-425
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- Hideyuki Ichihara, Masakuni Ochi, Michihiro Shintani, Tomoo Inoue:
A Test Decompression Scheme for Variable-Length Coding.
426-431
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- Youhua Shi, Shinji Kimura, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
Alternative Run-Length Coding through Scan Chain Reconfiguration for Joint Minimization of Test Data Volume and Power Consumption in Scan Test.
432-437
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Session C6:
Delay Testing
Copyright © Sat May 16 22:59:04 2009
by Michael Ley (ley@uni-trier.de)
