Volume 22,
Number 1,
January 2003
- Jong-Yeol Lee, In-Cheol Park:
Timed compiled-code functional simulation of embedded software for performance analysis of SOC design.
1-14
Electronic Edition (link) BibTeX
- David J. Walkey, Dritan Celo, Tom J. Smy:
A simplified model for the effect of interfinger metal on maximum temperature rise in a multifinger bipolar transistor.
15-25
Electronic Edition (link) BibTeX
- Nikolay Rubanov:
SubIslands: the probabilistic match assignment algorithm for subcircuit recognition.
26-38
Electronic Edition (link) BibTeX
- David Blaauw, Chanhee Oh, Vladimir Zolotov, Aurobindo Dasgupta:
Static electromigration analysis for on-chip signal interconnects.
39-48
Electronic Edition (link) BibTeX
- Haitian Hu, David T. Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar:
Fast on-chip inductance simulation using a precorrected-FFT method.
49-66
Electronic Edition (link) BibTeX
- Jaesik Lee, Ki-Wook Kim, Yoonjong Huh, Peter Bendix, Sung-Mo Kang:
Chip-level charged-device modeling and simulation in CMOS integrated circuits.
67-81
Electronic Edition (link) BibTeX
- Irith Pomeranz, Sudhakar M. Reddy:
Test enrichment for path delay faults using multiple sets of target faults.
82-90
Electronic Edition (link) BibTeX
- Li-Da Huang, Minghorng Lai, Martin D. F. Wong, Youxin Gao:
Maze routing with buffer insertion under transition time constraints.
91-95
Electronic Edition (link) BibTeX
- Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang:
Timing constraints for domino logic gates with timing-dependent keepers.
96-103
Electronic Edition (link) BibTeX
- Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou:
Automatic interconnection rectification for SoC design verification based on the port order fault model.
104-114
Electronic Edition (link) BibTeX
Volume 22,
Number 2,
February 2003
- H. Alan Mantooth, Georges G. E. Gielen:
Guest editorial.
121-123
Electronic Edition (link) BibTeX
- Manuel Innocent, Piet Wambacq, Stéphane Donnay, Harrie A. C. Tilmans, Willy M. C. Sansen, Hugo De Man:
An analytic Volterra-series-based model for a MEMS variable capacitor.
124-131
Electronic Edition (link) BibTeX
- Patrick Reynaert, Koen L. R. Mertens, Michiel Steyaert:
A state-space behavioral model for CMOS class E power amplifiers.
132-138
Electronic Edition (link) BibTeX
- Steven P. Levitan, Jose A. Martinez, Timothy P. Kurzweg, Abhijit Davare, Mark Kahrs, Michael Bails, Donald M. Chiarulli:
System simulation of mixed-signal multi-domain microsystems with piecewise linear models.
139-154
Electronic Edition (link) BibTeX
- Michal Rewienski, Jacob K. White:
A trajectory piecewise-linear approach to model order reduction and fast simulation of nonlinear circuits and micromachined devices.
155-170
Electronic Edition (link) BibTeX
- Joel R. Phillips:
Projection-based approaches for model reduction of weakly nonlinear, time-varying systems.
171-187
Electronic Edition (link) BibTeX
- Alper Demir, Jaijeet S. Roychowdhury:
A reliable and efficient procedure for oscillator PPV computation, with phase noise macromodeling applications.
188-197
Electronic Edition (link) BibTeX
- Glenn Wolfe, Ranga Vemuri:
Extraction and use of neural network models in automated synthesis of operational amplifiers.
198-212
Electronic Edition (link) BibTeX
- Bart De Smedt, Georges G. E. Gielen:
WATSON: design space boundary exploration and model generation for analog and RFIC design.
213-224
Electronic Edition (link) BibTeX
- David Binkley, C. E. Hopper, Steve D. Tucker, Brian C. Moss, James M. Rochelle, Daniel Foty:
A CAD methodology for optimizing transistor current and sizing in analog CMOS design.
225-237
Electronic Edition (link) BibTeX
Volume 22,
Number 3,
Mar 2003
- Charles J. Alpert, Andrew B. Kahng, Bao Liu, Ion I. Mandoiu, Alexander Zelikovsky:
Minimum buffered routing with bounded capacitive load for slew rate and reliability control.
241-253
Electronic Edition (link) BibTeX
- Mary Y. L. Wisniewski, Emmanuel Yashchin, Robert L. Franch, David P. Conrady, Daniel N. Maynard, Giovanni Fiorenza, I. Cevdet Noyan:
The physical design of on-chip interconnections.
254-276
Electronic Edition (link) BibTeX
- Sheldon X.-D. Tan, C.-J. Richard Shi:
Efficient very large scale integration power/ground network sizing based on equivalent circuit modeling.
277-284
Electronic Edition (link) BibTeX
- Clemens Heitzinger, Wolfgang Pyka, Naoki Tamaoki, Toshiro Takase, Toshimitsu Ohmine, Siegfried Selberherr:
Simulation of arsenic in situ doping with polysilicon CVD and its application to high aspect ratio trenches.
285-292
Electronic Edition (link) BibTeX
- Ruifeng Guo, Sudhakar M. Reddy, Irith Pomeranz:
Reverse-order-restoration-based static test compaction for synchronous sequential circuits.
293-304
Electronic Edition (link) BibTeX
- Saravanan Padmanaban, Maria K. Michael, Spyros Tragoudas:
Exact path delay fault coverage with fundamental ZBDD operations.
305-316
Electronic Edition (link) BibTeX
- Kianosh Rahimi, Mani Soma:
Layout driven synthesis of multiple scan chains.
317-326
Electronic Edition (link) BibTeX
- Yuejian Wu, Paul N. MacDonald:
Testing ASICs with multiple identical cores.
327-336
Electronic Edition (link) BibTeX
- Murat R. Becer, David T. Blaauw, Rajendran Panda, Ibrahim N. Hajj:
Early probabilistic noise estimation for capacitively coupled interconnects.
337-345
Electronic Edition (link) BibTeX
- Noureddine Chabini, Ismaïl Chabini, El Mostapha Aboulhamid, Yvon Savaria:
Methods for minimizing dynamic power consumption in synchronous designs with multiple supply voltages.
346-351
Electronic Edition (link) BibTeX
- Anshuman Chandra, Krishnendu Chakrabarty:
A unified approach to reduce SOC test data volume, scan power and testing time.
352-363
Electronic Edition (link) BibTeX
- Jih-Jeen Chen, Chia-Kai Yang, Kuen-Jong Lee:
Test pattern generation and clock disabling for simultaneous test time and power reduction.
363-370
Electronic Edition (link) BibTeX
- James F. Plusquellic, Abhishek Singh, Chintan Patel, Anne E. Gattiker:
Power supply transient signal analysis for defect-oriented test.
370-374
Electronic Edition (link) BibTeX
- Qiushuang Zhang, Ian G. Harris:
Partial BIST insertion to eliminate data correlation.
374-379
Electronic Edition (link) BibTeX
Volume 22,
Number 4,
April 2003
- Charles J. Alpert, Sachin S. Sapatnekar:
Guest editorial.
385-386
Electronic Edition (link) BibTeX
- Ulrich Brenner, André Rohe:
An effective congestion-driven placement framework.
387-394
Electronic Edition (link) BibTeX
- Chin-Chih Chang, Jason Cong, David Zhigang Pan, Xin Yuan:
Multilevel global placement with congestion control.
395-409
Electronic Edition (link) BibTeX
- Xiaojian Yang, Bo-Kyung Choi, Majid Sarrafzadeh:
Routability-driven white space allocation for fixed-die standard-cell placement.
410-419
Electronic Edition (link) BibTeX
- Yongseok Cheon, Martin D. F. Wong:
Design hierarchy-guided multilevel circuit partitioning.
420-427
Electronic Edition (link) BibTeX
- Haihua Su, Sachin S. Sapatnekar, Sani R. Nassif:
Optimal decoupling capacitor sizing and placement for standard-cell layout designs.
428-436
Electronic Edition (link) BibTeX
- Prashant Saxena, Satyanarayan Gupta:
On integrating power and signal routing for shield count minimization in congested regions.
437-445
Electronic Edition (link) BibTeX
- Shuo Zhang, Wayne Wei-Ming Dai:
TEG: a new post-layout optimization method.
446-456
Electronic Edition (link) BibTeX
- Evangeline F. Y. Young, Chris C. N. Chu, Zion Cien Shen:
Twin binary sequences: a nonredundant representation for general nonslicing floorplan.
457-469
Electronic Edition (link) BibTeX
- Chiu-Wing Sham, Evangeline F. Y. Young:
Routability-driven floorplanner with buffer block planning.
470-480
Electronic Edition (link) BibTeX
- Milos Hrkic, John Lillis:
Buffer tree synthesis with consideration of temporal locality, sink polarity requirements, solution cost, congestion, and blockages.
481-491
Electronic Edition (link) BibTeX
- Jiang Hu, Charles J. Alpert, Stephen T. Quay, Gopal Gandham:
Buffer insertion with adaptive blockage avoidance.
492-498
Electronic Edition (link) BibTeX
- Davide Pandini, Lawrence T. Pileggi, Andrzej J. Strojwas:
Global and local congestion optimization in technology mapping.
498-505
Electronic Edition (link) BibTeX
- Seokjin Lee, Martin D. F. Wong:
Timing-driven routing for FPGAs based on Lagrangian relaxation.
506-510
Electronic Edition (link) BibTeX
Volume 22,
Number 5,
May 2003
- Walter Daems, Georges G. E. Gielen, Willy M. C. Sansen:
Simulation-based generation of posynomial performance models for the sizing of analog integrated circuits.
517-534
Electronic Edition (link) BibTeX
- Jovanka Ciric, Carl Sechen:
Efficient canonical form for Boolean matching of complex functions in large libraries.
535-544
Electronic Edition (link) BibTeX
- Srini Krishnamoorthy, Russell Tessier:
Technology mapping algorithms for hybrid FPGAs containing lookup tables and PLAs.
545-559
Electronic Edition (link) BibTeX
- Takashi Sato, Yu Cao, Kanak Agarwal, Dennis Sylvester, Chenming Hu:
Bidirectional closed-form transformation between on-chip coupling noise waveforms and interconnect delay-change curves.
560-572
Electronic Edition (link) BibTeX
- Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Paul Villarrubia:
A practical methodology for early buffer and wire resource allocation.
573-583
Electronic Edition (link) BibTeX
- Jae-Gon Kim, Yeong-Dae Kim:
A linear programming-based algorithm for floorplanning in VLSI design.
584-592
Electronic Edition (link) BibTeX
- Chunsheng Liu, Krishnendu Chakrabarty:
Failing vector identification based on overlapping intervals of test vectors in a scan-BIST environment.
593-604
Electronic Edition (link) BibTeX
- Elaheh Bozorgzadeh, Ryan Kastner, Majid Sarrafzadeh:
Creating and exploiting flexibility in rectilinear Steiner trees.
605-615
Electronic Edition (link) BibTeX
- Robert P. Dick, Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha:
Analysis of power dissipation in embedded systems using real-time operating systems.
615-627
Electronic Edition (link) BibTeX
- Li Ding, David T. Blaauw, Pinaki Mazumder:
Accurate crosstalk noise modeling for early signal integrity analysis.
627-634
Electronic Edition (link) BibTeX
- Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen:
Efficient test access mechanism optimization for system-on-chip.
635-643
Electronic Edition (link) BibTeX
- Louis Scheffer:
Some conditions under which hierarchical verification is O(N).
643-646
Electronic Edition (link) BibTeX
- Cliff C. N. Sze, Ting-Chi Wang:
Optimal circuit clustering for delay minimization under a more general delay model.
646-651
Electronic Edition (link) BibTeX
- Wing Seung Yuen, Evangeline F. Y. Young:
Slicing floorplan with clustering constraint.
652-658
Electronic Edition (link) BibTeX
Volume 22,
Number 6,
June 2003
- Soha Hassoun, Steven M. Nowick, Leon Stok:
Guest Editorial.
662-664
Electronic Edition (link) BibTeX
- Prabhakar Kudva, Andrew Sullivan, William E. Dougherty:
Measurements for structural logic synthesis optimizations.
665-674
Electronic Edition (link) BibTeX
- Jordi Cortadella:
Timing-driven logic bi-decomposition.
675-685
Electronic Edition (link) BibTeX
- Jie-Hong Roland Jiang, Robert K. Brayton:
On the verification of sequential equivalence.
686-697
Electronic Edition (link) BibTeX
- Amit Prakash, Ramakrishna Kotla, Tanmoy Mandal, Adnan Aziz:
A high-performance architecture and BDD-based synthesis methodology for packet classification.
698-709
Electronic Edition (link) BibTeX
- Vivek V. Shende, Aditya K. Prasad, Igor L. Markov, John P. Hayes:
Synthesis of reversible logic circuits.
710-722
Electronic Edition (link) BibTeX
- Fan Mo, Robert K. Brayton:
PLA-based regular structures and their synthesis.
723-729
Electronic Edition (link) BibTeX
- Faran Rafiq, Malgorzata Chrzanowska-Jeske, Hannah Honghua Yang, Marcin Jeske, Naveed A. Sherwani:
Integrated floorplanning with buffer/channel insertion for bus-based designs.
730-741
Electronic Edition (link) BibTeX
- H. C. Srinivasaiah, Navakanta Bhat:
Mixed-mode simulation approach to characterize the circuit delay sensitivity to implant dose variations.
742-747
Electronic Edition (link) BibTeX
- Tingdong Zhou, Steven L. Dvorak, John L. Prince:
Lossy transmission line simulation based on closed-form triangle impulse responses.
748-755
Electronic Edition (link) BibTeX
- Jing-Jia Liou, Angela Krstic, Yi-Min Jiang, Kwang-Ting Cheng:
Modeling, testing, and analysis for delay defects and noise effects in deep submicron devices.
756-769
Electronic Edition (link) BibTeX
- Yi Zhao, Sujit Dey:
Fault-coverage analysis techniques of crosstalk in chip interconnects.
770-782
Electronic Edition (link) BibTeX
- Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici:
Variable-length input Huffman coding for system-on-a-chip test.
783-796
Electronic Edition (link) BibTeX
- Abhijit Jas, Jayabrata Ghosh-Dastidar, Mom-Eng Ng, Nur A. Touba:
An efficient test vector compression scheme using selective Huffman coding.
797-806
Electronic Edition (link) BibTeX
- Arlindo L. Oliveira, Rajeev Murgai:
On the problem of gate assignment under different rise and fall delays.
807-814
Electronic Edition (link) BibTeX
- Hui Xu, Rob A. Rutenbar, Karem A. Sakallah:
sub-SAT: a formulation for relaxed Boolean satisfiability with applications in routing.
814-820
Electronic Edition (link) BibTeX
Volume 22,
Number 7,
July 2003
- Ingmar Neumann, Wolfgang Kunz:
Layout driven retiming using the coupled edge timing model.
825-835
Electronic Edition (link) BibTeX
- Zhan Yu, Kei-Yong Khoo, Alan N. Willson Jr.:
Optimal joint module-selection and retiming with carry-save representation.
836-846
Electronic Edition (link) BibTeX
- Vishnu Swaminathan, Krishnendu Chakrabarty:
Energy-conscious, deterministic I/O device scheduling in hard real-time systems.
847-858
Electronic Edition (link) BibTeX
- Sarnath Ramnath:
New approximations for the rectilinear Steiner arborescence problem [VLSI layout].
859-869
Electronic Edition (link) BibTeX
- Hua Xiang, Xiaoping Tang, Martin D. F. Wong:
Min-cost flow-based algorithm for simultaneous pin assignment and routing.
870-878
Electronic Edition (link) BibTeX
- Clemens Heitzinger, Andreas Hössinger, Siegfried Selberherr:
On smoothing three-dimensional Monte Carlo ion implantation simulation results.
879-883
Electronic Edition (link) BibTeX
- Tsung-Hao Chen, Clement Luk, Charlie Chung-Ping Chen:
INDUCTWISE: inductance-wise interconnect simulator and extractor.
884-894
Electronic Edition (link) BibTeX
- Xiaoling Huang, Chris S. Gathercole, H. Alan Mantooth:
Modeling nonlinear dynamics in analog circuits via root localization.
895-907
Electronic Edition (link) BibTeX
- Per Gunnar Kjeldsberg, Francky Catthoor, Einar J. Aas:
Data dependency size estimation for use in memory optimization.
908-921
Electronic Edition (link) BibTeX
- Enamul Amyeen, W. Kent Fuchs, Irith Pomeranz, Vamsi Boppana:
Fault equivalence identification in combinational circuits using implication and evaluation techniques.
922-936
Electronic Edition (link) BibTeX
- Christoph Albrecht, Andrew B. Kahng, Bao Liu, Ion I. Mandoiu, Alexander Zelikovsky:
On the skew-bounded minimum-buffer routing tree problem.
937-945
Electronic Edition (link) BibTeX
- Chih-Wei Jim Chang, Ming-Fu Hsiao, Malgorzata Marek-Sadowska:
A new reasoning scheme for efficient redundancy addition and removal.
945-951
Electronic Edition (link) BibTeX
- Wai-Kei Mak, Evangeline F. Y. Young:
Temporal logic replication for dynamically reconfigurable FPGA partitioning.
952-959
Electronic Edition (link) BibTeX
Volume 22,
Number 8,
August 2003
- David T. Blaauw, Luciano Lavagno:
Guest Editorial.
962-963
Electronic Edition (link) BibTeX
- Armita Peymandoust, Tajana Simunic, Giovanni De Micheli:
Complex instruction and software library mapping for embedded software using symbolic algebra.
964-975
Electronic Edition (link) BibTeX
- Yoonseo Choi, Taewhan Kim:
Address assignment in DSP code generation - an integrated approach.
976-984
Electronic Edition (link) BibTeX
- Michael J. Wirthlin, Brian McMurtrey:
Web-based IP evaluation and distribution using applets.
985-994
Electronic Edition (link) BibTeX
- Fadi A. Aloul, Brian D. Sierawski, Karem A. Sakallah:
Satometer: how much have we searched?
995-1004
Electronic Edition (link) BibTeX
- Anna Bernasconi, Valentina Ciriani, Fabrizio Luccio, Linda Pagli:
Three-level logic minimization based on function regularities.
1005-1016
Electronic Edition (link) BibTeX
- Piet Vanassche, Georges G. E. Gielen, Willy M. C. Sansen:
Behavioral modeling of (coupled) harmonic oscillators.
1017-1026
Electronic Edition (link) BibTeX
- Joel R. Phillips, Luca Daniel, Luis Miguel Silveira:
Guaranteed passive balancing transformations for model order reduction.
1027-1041
Electronic Edition (link) BibTeX
- Gunnar Andersson, Per Bjesse, Byron Cook, Ziyad Hanna:
Design automation with mixtures of proof strategies for propositional logic.
1042-1048
Electronic Edition (link) BibTeX
- Kenneth Francken, Georges G. E. Gielen:
A high-level simulation and synthesis environment for /spl Delta//spl Sigma/ modulators.
1049-1061
Electronic Edition (link) BibTeX
- Gang Quan, Xiaobo Sharon Hu:
Minimal energy fixed-priority scheduling for variable voltage processors.
1062-1071
Electronic Edition (link) BibTeX
- Paolo Pavan, Luca Larcher, Massimiliano Cuozzo, Paola Zuliani, Antonino Conte:
A complete model of E2PROM memory cells for circuit simulations.
1072-1079
Electronic Edition (link) BibTeX
- Ruifeng Guo, Sudhakar M. Reddy, Irith Pomeranz:
PROPTEST: a property-based test generator for synchronous sequential circuits.
1080-1091
Electronic Edition (link) BibTeX
- Irith Pomeranz, Sudhakar M. Reddy:
Theorems for identifying undetectable faults in partial-scan circuits.
1092-1097
Electronic Edition (link) BibTeX
- Joon-Jea Sung, Guen-Soon Kang, Suki Kim:
A transient noise model for frequency-dependent noise sources.
1097-1104
Electronic Edition (link) BibTeX
- Pradip A. Thaker, Vishwani D. Agrawal, Mona E. Zaghloul:
A test evaluation technique for VLSI circuits using register-transfer level fault modeling.
1104-1113
Electronic Edition (link) BibTeX
Volume 22,
Number 9,
September 2003
- Fadi A. Aloul, Arathi Ramani, Igor L. Markov, Karem A. Sakallah:
Solving difficult instances of Boolean satisfiability in the presence of symmetry.
1117-1137
Electronic Edition (link) BibTeX
- Hao Zheng, Eric Mercer, Chris J. Myers:
Modular verification of timed circuits using automatic abstraction.
1138-1153
Electronic Edition (link) BibTeX
- Armita Peymandoust, Giovanni De Micheli:
Application of symbolic computer algebra in high-level data-flow synthesis.
1154-1165
Electronic Edition (link) BibTeX
- Debatosh Debnath, Zvonko G. Vranesic:
A fast algorithm for OR-AND-OR synthesis.
1166-1176
Electronic Edition (link) BibTeX
- Adnan Kabbani, Dhamin Al-Khalili, Asim J. Al-Khalili:
Technology-portable analytical model for DSM CMOS inverter transition-time estimation.
1177-1187
Electronic Edition (link) BibTeX
- Sarma B. K. Vrudhula, David T. Blaauw, Supamas Sirichotiyakul:
Probabilistic analysis of interconnect coupling noise.
1188-1203
Electronic Edition (link) BibTeX
- Thomas Binder, Andreas Hössinger, Siegfried Selberherr:
Rigorous integration of semiconductor process and device simulators.
1204-1214
Electronic Edition (link) BibTeX
- Petr Dobrovolný, Gerd Vandersteen, Piet Wambacq, Stéphane Donnay:
Analysis and compact behavioral modeling of nonlinear distortion in analog communication circuits.
1215-1227
Electronic Edition (link) BibTeX
- Gang Li, Narayan R. Aluru:
Efficient mixed-domain analysis of electrostatic MEMS.
1228-1242
Electronic Edition (link) BibTeX
- Aseem Agarwal, Vladimir Zolotov, David T. Blaauw:
Statistical timing analysis using bounds and selective enumeration.
1243-1260
Electronic Edition (link) BibTeX
- Hai Zhou:
Timing analysis with crosstalk is a fixpoint on a complete lattice.
1261-1269
Electronic Edition (link) BibTeX
- Soha Hassoun, Christopher Cromer, Eduardo Calvillo-Gámez:
Static timing analysis for level-clocked circuits in the presence of crosstalk.
1270-1277
Electronic Edition (link) BibTeX
- Darko Kirovski, Miodrag Potkonjak:
Local watermarks: methodology and application to behavioral synthesis.
1277-1283
Electronic Edition (link) BibTeX
- Tat Kee Tan, Anand Raghunathan, Niraj K. Jha:
A simulation framework for energy-consumption analysis of OS-driven embedded applications.
1284-1294
Electronic Edition (link) BibTeX
Volume 22,
Number 10,
October 2003
- Peng Li, Lawrence T. Pileggi:
Efficient per-nonlinearity distortion analysis for analog and RF circuits.
1297-1309
Electronic Edition (link) BibTeX
- Valentina Ciriani:
Synthesis of SPP three-level logic networks using affine spaces.
1310-1323
Electronic Edition (link) BibTeX
- Mohab Anis, Shawki Areibi, Mohamed I. Elmasry:
Design and optimization of multithreshold CMOS (MTCMOS) circuits.
1324-1342
Electronic Edition (link) BibTeX
- Charles J. Alpert, Gi-Joon Nam, Paul G. Villarrubia:
Effective free space management for cut-based placement via analytical constraint generation.
1343-1353
Electronic Edition (link) BibTeX
- Zion Cien Shen, Chris C. N. Chu:
Bounds on the number of slicing, mosaic, and general floorplans.
1354-1361
Electronic Edition (link) BibTeX
- Rouying Zhan, Haigang Feng, Qiong Wu, Haolu Xie, Xiaokang Guan, Guang Chen, Albert Z. Wang:
ESDExtractor: A new technology-independent CAD tool for arbitrary ESD protection device extraction.
1362-1370
Electronic Edition (link) BibTeX
- Zaid Al-Ars, A. J. van de Goor:
Test generation and optimization for DRAM cell defects using electrical simulation.
1371-1384
Electronic Edition (link) BibTeX
- Junwei Hou, Abhijit Chatterjee:
Concurrent transient fault simulation for analog circuits.
1385-1398
Electronic Edition (link) BibTeX
- Saravanan Padmanaban, Spyros Tragoudas:
An implicit path-delay fault diagnosis methodology.
1399-1408
Electronic Edition (link) BibTeX
- Jeongjin Roh, Jacob A. Abraham:
A comprehensive signature analysis scheme for oscillation-test.
1409-1423
Electronic Edition (link) BibTeX
- Deming Chen, Jason Cong, Milos D. Ercegovac, Zhijun Huang:
Performance-driven mapping for CPLD architectures.
1424-1431
Electronic Edition (link) BibTeX
- George A. Constantinides, Peter Y. K. Cheung, Wayne Luk:
Wordlength optimization for linear digital signal processing.
1432-1442
Electronic Edition (link) BibTeX
- Michael Dimopoulos, Panagiotis Linardis:
Accelerating the compaction of test sequences in sequential circuits through problem size reduction.
1443-1449
Electronic Edition (link) BibTeX
- Irith Pomeranz, Sudhakar M. Reddy:
Test data compression based on input-output dependence.
1450-1455
Electronic Edition (link) BibTeX
Volume 22,
Number 11,
November 2003
- Cesare Alippi, Andrea Galbusera, Marco Stellini:
An application-level synthesis methodology for multidimensional embedded processing systems.
1457-1470
Electronic Edition (link) BibTeX
- Peter M. Maurer:
Efficient event-driven simulation by exploiting the output observability of gate clusters.
1471-1486
Electronic Edition (link) BibTeX
- Junhyung Um, Taewhan Kim:
Synthesis of arithmetic circuits considering layout effects.
1487-1503
Electronic Edition (link) BibTeX
- Alex Doboli, Ranga Vemuri:
Behavioral modeling for high-level synthesis of analog and mixed-signal systems from VHDL-AMS.
1504-1520
Electronic Edition (link) BibTeX
- Guoan Zhong, Cheng-Kok Koh, Kaushik Roy:
On-chip interconnect modeling by wire duplication.
1521-1532
Electronic Edition (link) BibTeX
- Haihua Su, Kaushik Gala, Sachin S. Sapatnekar:
Analysis and optimization of structured power/ground networks.
1533-1544
Electronic Edition (link) BibTeX
- Yu-Min Lee, Charlie Chung-Ping Chen:
The power grid transient simulation in linear time based on 3-D alternating-direction-implicit method.
1545-1550
Electronic Edition (link) BibTeX
- Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov:
Hierarchical whitespace allocation in top-down placement.
1550-1556
Electronic Edition (link) BibTeX
- Alex Doboli, Ranga Vemuri:
Exploration-based high-level synthesis of linear analog systems operating at low/medium frequencies.
1556-1568
Electronic Edition (link) BibTeX
- Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici:
Addressing useless test data in core-based system-on-a-chip test.
1568-1580
Electronic Edition (link) BibTeX
- Soha Hassoun, Charles J. Alpert:
Optimal path routing in single- and multiple-clock domain systems.
1580-1588
Electronic Edition (link) BibTeX
- Alan Mishchenko:
Fast computation of symmetries in Boolean functions.
1588-1593
Electronic Edition (link) BibTeX
Volume 22,
Number 12,
December 2003
- Frederic Doucet, Sandeep K. Shukla, Masato Otsuka, Rajesh K. Gupta:
BALBOA: a component-based design environment for system models.
1597-1612
Electronic Edition (link) BibTeX
- Pasquale Cocchini:
A methodology for optimal repeater insertion in pipelined interconnects.
1613-1624
Electronic Edition (link) BibTeX
- Giorgio Casinovi, Chad Young:
Estimation of power dissipation in switched-capacitor circuits.
1625-1636
Electronic Edition (link) BibTeX
- Hongbing Fan, Jiping Liu, Yu-Liang Wu, Chak-Chung Cheung:
On optimal hyperuniversal and rearrangeable switch box designs.
1637-1649
Electronic Edition (link) BibTeX
- Hendrik Rogier, Daniel De Zutter:
A fast technique based on perfectly matched layers for the full-wave solution of 2-D dispersive microstrip lines.
1650-1656
Electronic Edition (link) BibTeX
- Rüdiger Ebendt, Wolfgang Günther, Rolf Drechsler:
An improved branch and bound algorithm for exact BDD minimization.
1657-1663
Electronic Edition (link) BibTeX
- Irith Pomeranz, Sudhakar M. Reddy:
Transparent scan: a new approach to test generation and test compaction for scan circuits that incorporates limited scan operations.
1663-1670
Electronic Edition (link) BibTeX
- Peyman Rezvani, Massoud Pedram:
A fanout optimization algorithm based on the effort delay model.
1671-1678
Electronic Edition (link) BibTeX
- Sheldon X.-D. Tan, C.-J. Richard Shi, Jyh-Chwen Lee:
Reliability-constrained area optimization of VLSI power/ground networks via sequence of linear programmings.
1678-1684
Electronic Edition (link) BibTeX
- Teng-Sheng Moh, Tsu-Shuan Chang:
Comments on "Handling soft modules in general nonslicing floorplan using Lagrangian relaxation".
1684-1686
Electronic Edition (link) BibTeX
Copyright © Sun May 17 00:23:13 2009
by Michael Ley (ley@uni-trier.de)