VTS 1999:
San Diego,
CA,
USA
17th IEEE VLSI Test Symposium (VTS '99), 25-30 April 1999, San Diego, CA, USA.
IEEE Computer Society 1999, ISBN 0-7695-0146-X BibTeX
Keynote Address
Invited Presentation
Testing High-Speed and Dynamic Circuits
Core Testing
Diagnosis
Techniques for the Very-Deep Submicron
Advanced Scan Path Techniques
IDDQ Testing
Delay Fault Testing
Validation,
Verification,
and Diagnosis
Mixed Signal Testing
BIST
ATPG Related Approaches
- Ruifeng Guo, Irith Pomeranz, Sudhakar M. Reddy:
A Fault Simulation Based Test Pattern Generator for Synchronous Sequential Circuits.
260-267
Electronic Edition (link) BibTeX
- Michael R. Grimaila, Sooryong Lee, Jennifer Dworak, Kenneth M. Butler, Bret Stewart, Hari Balachandran, Bryan Houchins, Vineet Mathur, Jaehong Park, Li-C. Wang, M. Ray Mercer:
REDO - Probabilistic Excitation and Deterministic Observation - First Commercial Experimen.
268-274
Electronic Edition (link) BibTeX
- Sudhakar M. Reddy, Irith Pomeranz, Nadir Z. Basturkmen, Xijiang Lin:
Procedures for Identifying Undetectable and Redundant Faults In Synchronous Sequential Circuits.
275-283
Electronic Edition (link) BibTeX
Testing MEMS,
MCM and Analog Circuits
Mixed Signal BIST
High-Level Test Techniques
Concurrent Checking
Memory Test:
Moderators
BIST Related Approaches
Defect Oriented Test
On-Line Testing and Fault Tolerance
DFT and Boundary Scan
Copyright © Sat May 16 23:47:02 2009
by Michael Ley (ley@uni-trier.de)