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VTS 2001: Marina Del Rey, CA, USA

19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April - 3 May 2001, Marina Del Rey, CA, USA. IEEE Computer Society 2001, ISBN 0-7695-1122-8 BibTeX

BIST Techniques

Diagnosis Methods

Test Data Compression

Sythesis & Design for Testability

Scan Chain Design

Innovative Measurement Techniques

Diagnosis & Verification ATPG

Defect Analysis and IDDx Diagnosis


Hot Topic Session

SOC Testing

Online Testing

Self-Test Techniques

Memory Testing

Scalable Fault Simulation, Model Build and ATPG Methods

Test Stimulus Generation for Analog Testing

Hot Topic Session

Embedded Tutorial


Memory Diagnosis

Minimizing Test Power

Estimating and Reducing Infant Mortality

Novel ATPG Techniques

Test Scheduling, Leakage Estimation and Onchip Delay Measurement

Fault Modeling and BIST Evaluation



Copyright © Sat May 16 23:47:01 2009 by Michael Ley (ley@uni-trier.de)