VTS 2001: Marina Del Rey, CA, USA

19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April - 3 May 2001, Marina Del Rey, CA, USA. IEEE Computer Society 2001, ISBN 0-7695-1122-8 BibTeX

BIST Techniques

Abhijit Jas, C. V. Krishna, Nur A. Touba:
Hybrid BIST Based on Weighted Pseudo-Random Testing: A New Test Resource Partitioning Scheme. 2-8
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Douglas Kay, Samiha Mourad:
Compression Technique for Interactive BIST Application. 9-14
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Mihalis Psarakis, Antonis M. Paschalis, Nektarios Kranitis, Dimitris Gizopoulos, Yervant Zorian:
Robust and Low-Cost BIST Architectures for Sequential Fault Testing in Datapath Multipliers. 15-21
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Diagnosis Methods

Chien-Mo James Li, Edward J. McCluskey:
Diagnosis of Tunneling Opens. 22-27
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Ramesh C. Tekumalla, Srikanth Venkataraman, Jayabrata Ghosh-Dastidar:
On Diagnosing Path Delay Faults in an At-Speed Environment. 28-33
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Shi-Yu Huang:
On Improving the Accuracy Of Multiple Defect Diagnosis. 34-41
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Test Data Compression

Anshuman Chandra, Krishnendu Chakrabarty:
Frequency-Directed Run-Length (FDR) Codes with Application to System-on-a-Chip Test Data Compression. 42-47
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A. Morozov, Michael Gössel, Krishnendu Chakrabarty, Bhargab B. Bhattacharya:
Design of Parameterizable Error-Propagating Space Compactors for Response Observation. 48-53
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Aiman El-Maleh, Esam Khan, Saif al Zahir:
A Geometric-Primitives-Based Compression Scheme for Testing Systems-on-a-Chip. 54-61
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Sythesis & Design for Testability

Richard M. Chou, Kewal K. Saluja:
Testable Sequential Circuit Design: A Partition and Resynthesis Approach. 62-67
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Muhammad Nummer, Manoj Sachdev:
A Methodology for Testing High-Performance Circuits at Arbitrarily Low Test Frequency. 68-74
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Kelly A. Ockunzzi, Christos A. Papachristou:
Breaking Correlation to Improve Testability. 75-81
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Scan Chain Design

Dong Xiang, Yi Xu:
Partial Reset for Synchronous Sequential Circuits Using Almost Independent Reset Signals. 82-87
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Ilia Polian, Bernd Becker:
Multiple Scan Chain Design for Two-Pattern Testing. 88-93
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Dilip K. Bhavsar:
Scan Wheel - A Technique for Interfacing a High Speed Scan-Path with a Slow Speed Tester. 94-101
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Innovative Measurement Techniques

Takahiro J. Yamaguchi, Masahiro Ishida, Mani Soma, David Halter, Rajesh Raina, Jim Nissen:
A Method for Measuring the Cycle-to-Cycle Period Jitter of High-Frequency Clock Signals. 102-110
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Amir Attarha, Mehrdad Nourani:
Built-In-Chip Testing of Voltage Overshoots in High-Speed SoCs. 111-116
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Xiaoyun Sun, Bapiraju Vinnakota:
Current Measurement for Dynamic Idd Test. 117-123
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Diagnosis & Verification ATPG

Enamul Amyeen, W. Kent Fuchs, Irith Pomeranz, Vamsi Boppana:
Fault Equivalence Identification Using Redundancy Information and Static and Dynamic Extraction. 124-130
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Julia Dushina, Mike Benjamin, Daniel Geist:
Semi-Formal Test Generation for a Block of Industrial DSP. 131-137
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Defect Analysis and IDDx Diagnosis

Antonio Zenteno, Víctor H. Champac:
Resistive Opens in a Class of CMOS Latches: Analysis and DFT. 138-144
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Chintan Patel, Jim Plusquellic:
A Process and Technology-Tolerant IDDQ Method for IC Diagnosis. 145-152
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Panel

Bill Bottoms, Jim Chung, Bernd Koenemann, Glenn Shirley, Lisa Spainhower:
Guaranteeing Quality throughout the Product Life Cycle: On-Line Test and Repair to the Rescue. 153-154
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Hot Topic Session

Mike Rodgers:
ITRS Test Chapter 2001: We'll Tell You What We're Doing, You Tell Us What We Should Be Doing. 155-157
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SOC Testing

Tek Jau Tan, Chung-Len Lee:
Socillator Test: A Delay Test Scheme for Embedded ICs in the Boundary-Scan Environment. 158-162
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Ashish Giani, Shuo Sheng, Michael S. Hsiao, Vishwani D. Agrawal:
Novel Spectral Methods for Built-In Self-Test in a System-on-a-Chip Environment. 163-168
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Xiaoliang Bai, Sujit Dey:
High-level Crosstalk Defect Simulation for System-on-Chip Interconnects. 169-177
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Online Testing

Subhasish Mitra, Edward J. McCluskey:
Design Diversity for Concurrent Error Detection in Sequential Logic Circuts. 178-183
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Egor S. Sogomonyan, A. A. Morosov, Jan Rzeha, Michael Gössel, Adit D. Singh:
Early Error Detection in Systems-on-Chip for Fault-Tolerance and At-Speed Debugging. 184-189
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Subhasish Mitra, Edward J. McCluskey:
Design of Redundant Systems Protected Against Common-Mode Failures. 190-197
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Self-Test Techniques

Jing-Reng Huang, Madhu K. Iyer, Kwang-Ting Cheng:
A Self-Test Methodology for IP Cores in Bus-Based Programmable SoCs. 198-203
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Wei-Cheng Lai, Jing-Reng Huang, Kwang-Ting (Tim) Cheng:
Embedded-Software-Based Approach to Testing Crosstalk-Induced Faults at On-Chip Buses. 204-209
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Benoît Charlot, Salvador Mir, Fabien Parrain, Bernard Courtois:
Electrically Induced Stimuli For MEMS Self-Test. 210-217
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Memory Testing

Mohammad Gh. Mohammad, Kewal K. Saluja:
Flash Memory Disturbances: Modeling and Test. 218-224
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Kuo-Liang Cheng, Ming-Fu Tsai, Cheng-Wen Wu:
Efficient Neighborhood Pattern-Sensitive Fault Test Algorithms for Semiconductor Memories. 225-230
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Sultan M. Al-Harbi, Sandeep K. Gupta:
An Efficient Methodology for Generating Optimal and Uniform March Tests. 231-239
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Scalable Fault Simulation, Model Build and ATPG Methods

Ozgur Sinanoglu, Alex Orailoglu:
RT-level Fault Simulation Based on Symbolic Propagation. 240-245
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Yiorgos Makris, Vishal Patel, Alex Orailoglu:
Efficient Transparency Extraction and Utilization in Hierarchical Test. 246-251
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Magdy S. Abadir, Juhong Zhu, Li-C. Wang:
Analysis of Testing Methodologies for Custom Designs in PowerPCTM Microprocessor. 252-259
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Test Stimulus Generation for Analog Testing

Yue-Tsang Chen, Chauchin Su:
Test Waveform Shaping in Mixed Signal Test Bus by Pre-Equalization. 260-265
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Florence Azaïs, Serge Bernard, Yves Bertrand, Xavier Michel, Michel Renovell:
A Low-Cost Adaptive Ramp Generator for Analog BIST Applications. 266-271
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Eduardo J. Peralías, Gloria Huertas, Adoración Rueda, José L. Huertas:
Self-Testable Pipelined ADC with Low Hardware Overhead. 272-278
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Hot Topic Session

Jim Chung, N. Derhacobian, Jean Gasiot, Michael Nicolaidis, David Towne, R. Velazco:
Soft Errors and Tolerance for Soft Errors. 279-280
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Embedded Tutorial

Tracy Larrabee, Jon Colbum:
Yield Optimization and Its Relation to Test. 281-282
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Panel

Magdy S. Abadir, Scott Davidson, Vijay Nagasamy, Dhiraj K. Pradhan, Prab Varma:
ATPG for Design Errors-Is It Possible? 283-285
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Memory Diagnosis

Ivan de Paúl, M. Rosales, B. Alorda, Jaume Segura, Charles F. Hawkins, Jerry M. Soden:
Defect Oriented Fault Diagnosis for Semiconductor Memories using Charge Analysis: Theory and Experiments. 286-291
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John T. Chen, Wojciech Maly, Janusz Rajski, Omar Kebichi, Jitendra Khare:
Enabling Embedded Memory Diagnosis via Test Response Compression. 292-298
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Dirk Niggemeyer, Elizabeth M. Rudnick:
Automatic Generation of Diagnostic March Tests. 299-305
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Minimizing Test Power

Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Hans-Joachim Wunderlich:
A Modified Clock Scheme for a Low Power BIST Test Pattern Generator. 306-311
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Tobias Schüle, Albrecht P. Stroele:
Test Scheduling for Minimal Energy Consumption under Power Constraints. 312-318
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Ranganathan Sankaralingam, Nur A. Touba, Bahram Pouya:
Reducing Power Dissipation during Test Using Scan Chain Disable. 319-325
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Estimating and Reducing Infant Mortality

Thomas S. Barnett, Adit D. Singh, Victor P. Nelson:
Burn-In Failures and Local Region Yield: An Integrated Yield-Reliability Model. 326-332
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Mohammad Athar Khalil, Chin-Long Wey:
High-Voltage Stress Test Paradigms of Analog CMOS ICs for Gate-Oxide Reliability Enhancement. 333-338
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Chao-Wen Tseng, Ray Chen, Edward J. McCluskey, Phil Nigh:
MINVDD Testing for Weak CMOS ICs. 339-345
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Novel ATPG Techniques

Emil Gizdarski, Hideo Fujiwara:
SPIRIT: A Highly Robust Combinational Test Generation Algorithm. 346-351
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Irith Pomeranz, Sudhakar M. Reddy:
On the Use of Fault Dominance in n-Detection Test Generation. 352-357
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Yi-Shing Chang, Sandeep K. Gupta, Melvin A. Breuer:
Test Generation for Maximizing Ground Bounce for Internal Circuitry with Reconvergent Fan-out. 358-367
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Test Scheduling, Leakage Estimation and Onchip Delay Measurement

Vikram Iyengar, Krishnendu Chakrabarty:
Precedence-Based, Preemptive, and Power-Constrained Test Scheduling for System-on-a-Chip. 368-374
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José Pineda de Gyvez, Eric van de Wetering:
Average Leakage Current Estimation of CMOS Logic Circuits. 375-379
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Jiun-Lang Huang, Kwang-Ting Cheng:
An On-Chip Short-Time Interval Measurement Technique for Testing High-Speed Communication Links. 380-387
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Fault Modeling and BIST Evaluation

Ginette Monté, Bernard Antaki, Serge Patenaude, Yvon Savaria, Claude Thibeault, Pieter M. Trouborst:
Tools for the Characterization of Bipolar CML Testability. 388-395
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Keerthi Heragu, Manish Sharma, Rahul Kundu, R. D. (Shawn) Blanton:
Testing of Dynamic Logic Circuits Based on Charge Sharing. 396-403
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Chao-Wen Tseng, Subhasish Mitra, Edward J. McCluskey, Scott Davidson:
An Evaluation of Pseudo Random Testing for Detecting Real Defects. 404-410
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Showcase

Dwayne Burek, Garen Darbinyan, Rohit Kapur, Maurice Lousberg, Teresa L. McLaurin, Mike Ricchetti:
IP and Automation to Support IEEE P1500. 411-412
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Panels

Pete O'Neill, Ron Richmond, Mike Tripp, Barbara Vasquez, Art Wager, Zeev Weinberg:
Reliability Beyond GHz. 413-414
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Henry Chang, Steve Dollens, Gordon Roberts, Charles E. Stroud, Mani Soma, Jacob A. Abraham:
Analog and Mixed Signal Benchmark Circuit Development: Who Needs Them? 415-416
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