ED&TC 1997:
Paris,
France
European Design and Test Conference (ED&TC '97), Paris, France, 17-20 March 1997.
IEEE 1997 BibTeX
System Analysis Techniques and Applications
Sequential ATPG
Design and Design Methodology for Analog Circuits
Advances in Built-In Self-Test
Synthesis of Controllers
Microsystems Design I
- Klaus Hofmann, Manfred Glesner, Nicu Sebe, A. Manolescu, Santiago Marco, Josep Samitier, Jean-Michel Karam, Bernard Courtois:
Generation of the HDL-A-model of a micromembrane from its finite-element-description.
108-112
Electronic Edition (link) BibTeX
- S. Wünsche, C. Clauss, P. Schwarz, Frank Winkler:
Microsystem design using simulator coupling.
113-118
Electronic Edition (link) BibTeX
- B. Romanowicz, M. Laudon, P. Lerch, P. Renaud, Hans Peter Amann, A. Boegli, Vincent Moser, Fausto Pellandini:
Modeling and simulation of electromechanical transducers in microsystems using an analog hardware description language.
119-123
Electronic Edition (link) BibTeX
Software Generation for Embedded Processors
Register Transfer Level Test Synthesis
BDDs and Formal Verification
Microsystems Design II
High Performance Architectures for Multimedia and Communication ASICs
Decision Diagrams and Diagnosis
Performance Modeling
Progress in IDDQ Test Technology
Architecture Exploration
Layout Design
Testability Solutions for Regular Structures
Data Converter Test Issues
Extensions and Acceleration of Discrete Event Simulation
Analog Design and Layout Tools
Power Modeling and Estimation
Formal Methods in Synthesis and Verification
Concurrent Checking
New Ideas in Scheduling
System Level Design Representation and Transformation
Diagnosis and Test Generation
Logic Synthesis for Low Power
System Design Methodologies
Testability at Different Abstraction Levels
Hardware and Software Tools for Analog and Mixed-Signal Test
Power Estimation and Modeling
Posters
- Julio Faura, C. Horton, B. Krah, Joan Cabestany, M. A. Aguirre, Josep Maria Insenser:
A new field programmable system-on-a-chip for mixed signal integration.
610
Electronic Edition (link) BibTeX
- Jeroen A. J. Leijten, Jef L. van Meerbergen, Adwin H. Timmer, Jochen A. G. Jess:
PROPHID: a data-driven multi-processor architecture for high-performance DSP.
611
Electronic Edition (link) BibTeX
- Clifford Liem, Pierre G. Paulin, Ahmed Amine Jerraya:
ReCode: the design and re-design of the instruction codes for embedded instruction-set processors.
612
Electronic Edition (link) BibTeX
- T. Rowekamp, L. Peters:
A real-time smart sensor system for visual motion estimation.
613
Electronic Edition (link) BibTeX
- J. Gonzalez-Torres, P. A. Mateos, J. M. Hernandez:
Full custom chip set for high speed serial communications up to 2.48 Gbit/s.
614
Electronic Edition (link) BibTeX
- M. R. Karthikeyan, Soumitra Kumar Nandy:
An asynchronous architecture for digital signal processors.
615
Electronic Edition (link) BibTeX
- Hassan Ihs, Christian Dufaza:
Test synthesis for DC test of switched-capacitors circuits.
616
Electronic Edition (link) BibTeX
- Vladimir Székely, A. Pahi, András Poppe, Márta Rencz, A. Csendes:
SISSSI-A tool for dynamic electro-thermal simulation of analog VLSI cells.
617
Electronic Edition (link) BibTeX
- Marina Santo Zarnik, Franc Novak, Srecko Macek:
Design of oscillation-based test structures for active RC filters.
618
Electronic Edition (link) BibTeX
- Renate Beckmann, Jürgen Herrmann:
Using constraint logic programming in memory synthesis for general purpose computers.
619
Electronic Edition (link) BibTeX
- Igor Ozimek, R. Verlic, Jurij F. Tasic:
Optimal scheduling for fast systolic array implementations.
620
Electronic Edition (link) BibTeX
- Anne Mignotte, Olivier Peyran:
Scheduling using mixed arithmetic: an ILP formulation.
621
Electronic Edition (link) BibTeX
- Jeffrey Walrath, Ranga Vemuri, W. Bradley:
Performance verification using partial evaluation and interval analysis.
622
Electronic Edition (link) BibTeX
- A. Ursu, G. Gruita, S. Zaporojan:
Design and verification of the sequential systems automata using temporal logic specifications.
623
Electronic Edition (link) BibTeX
- Markus Wolf, Ulrich Kleine:
Application independent module generation in analog layouts.
624
Electronic Edition (link) BibTeX
- Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar:
A scheme for multiple on-chip signature checking for embedded SRAMs.
625
Electronic Edition (link) BibTeX
- Yoshinobu Higami, Kozo Kinoshita:
Design of partially parallel scan chain.
626
Electronic Edition (link) BibTeX
- A. J. van de Goor, Georgi Gaydadjiev, Vyacheslav N. Yarmolik, V. G. Mikitjuk:
March LA: a test for linked memory faults.
627
Electronic Edition (link) BibTeX
- Ronald D. Blanton, John P. Hayes:
The input pattern fault model and its application.
628
Electronic Edition (link) BibTeX
- M. Svajda, B. Straka, Hans A. R. Manhaeve:
A monolithic off-chip IDDQ monitor.
629
Electronic Edition (link) BibTeX
- Adam Kristof:
Extension of the boundary-scan architecture and new idea of BIST for more effective testing and self-testing of interconnections.
630
Electronic Edition (link) BibTeX
Copyright © Sat May 16 23:05:46 2009
by Michael Ley (ley@uni-trier.de)
