34. DAC 1997:
Anaheim,
California,
USA
Proceedings of the 34st Conference on Design Automation,
Anaheim,
California,
USA,
Anaheim Convention Center,
June 9-13,
1997. ACM Press,
1997,
ISBN 0-89791-920-3
Panel:
An Executive View of EDA Industry
Sequential Synthesis
- Naresh Maheshwari, Sachin S. Sapatnekar:
An Improved Algorithm for Minimum-Area Retiming.
2-7
Electronic Edition (ACM DL) BibTeX
- Ellen Sentovich, Horia Toma, Gérard Berry:
Efficient Latch Optimization Using Exclusive Sets.
8-11
Electronic Edition (ACM DL) BibTeX
- Diana Marculescu, Radu Marculescu, Massoud Pedram:
Sequence Compaction for Probabilistic Analysis of Finite-State Machines.
12-15
Electronic Edition (ACM DL) BibTeX
- Alexei L. Semenov, Alexandre Yakovlev, Enric Pastor, Marco A. Peña, Jordi Cortadella:
Synthesis of Speed-Independent Circuits from STG-Unfolding Segment.
16-21
Electronic Edition (ACM DL) BibTeX
- Luca Benini, Enrico Macii, Massimo Poncino:
Telescopic Units: Increasing the Average Throughput of Pipelined Designs by Adaptive Latency Control.
22-27
Electronic Edition (ACM DL) BibTeX
Interconnect Modeling
Novel Techniques for Software Scheduling
Embedded Tutorial:
Tools and Methodologies for Low Power Design
Panel:
Low-Power Design Tools - Where Is the Impact?
Simulation Techniques for Microprocessors
- Joon-Seo Yim, Yoon-Ho Hwang, Chang-Jae Park, Hoon Choi, Woo-Seung Yang, Hun-Seung Oh, In-Cheol Park, Chong-Min Kyung:
A C-Based RTL Design Verification Methodology for Complex Microprocessor.
83-88
Electronic Edition (ACM DL) BibTeX
- Jörg A. Walter, Jens Leenstra, Gerhard Döttling, Bernd Leppla, Hans-Jürgen Münster, Kevin W. Kark, Bruce Wile:
Hierarchical Random Simulation Approach for the Verification of S/390 CMOS Multiprocessors.
89-94
Electronic Edition (ACM DL) BibTeX
- Rajesh Raina, Robert Bailey, Charles Njinda, Robert F. Molyneaux, Charlie Beh:
Efficient Testing of Clock Regenerator Circuits in Scan Designs.
95-100
Electronic Edition (ACM DL) BibTeX
- Wen-Jong Fang, Allen C.-H. Wu, Ti-Yen Yen:
A Real-Time RTL Engineering-Change Method Supporting On-Line Debugging for Logic-Emulation Applications.
101-106
Electronic Edition (ACM DL) BibTeX
Combinational Logic Synthesis
Interconnect Parasitic Extraction
Advances in Timing Analysis for Embedded Software
Applications of Formal Verification
System-Level Exploration and Refinement
Binary Decision Diagrams
Timing Analysis
Tutorial:
Code Generation for Core Processors
Panel:
Physical Design and Synthesis:
Merge or Die!
System-Level Optimization and Verification
Formal Verification
Analog Simulation
Software Synthesis for Embedded Systems
- Ashok Sudarsanam, Stan Y. Liao, Srinivas Devadas:
Analysis and Evaluation of Address Arithmetic Capabilities in Custom DSP Architectures.
287-292
Electronic Edition (ACM DL) BibTeX
- Markus Willems, Volker Bürsgens, Holger Keding, Thorsten Grötker, Heinrich Meyr:
System Level Fixed-Point Design Based on an Interpolative Approach.
293-298
Electronic Edition (ACM DL) BibTeX
- George Hadjiyiannis, Silvina Hanono, Srinivas Devadas:
ISDL: An Instruction Set Description Language for Retargetability.
299-302
Electronic Edition (ACM DL) BibTeX
- Mark R. Hartoog, James A. Rowson, Prakash D. Reddy, Soumya Desai, Douglas D. Dunlop, Edwin A. Harcourt, Neeti Khullar:
Generation of Software Tools from Processor Descriptions for Hardware/Software Codesign.
303-306
Electronic Edition (ACM DL) BibTeX
Experiences in System Design and Education at Universities
Standard Cell and Physical Design Methods
- Hans T. Heineken, Jitendra Khare, Wojciech Maly, Pranab K. Nag, Charles H. Ouyang, Witold A. Pleskacz:
CAD at the Design-Manufacturing Interface.
321-326
Electronic Edition (ACM DL) BibTeX
- Mohankumar Guruswamy, Robert L. Maziasz, Daniel Dulitz, Srilata Raman, Venkat Chiluvuri, Andrea Fernandez, Larry G. Jones:
CELLERITY: A Fully Automatic Layout Synthesis System for Standard Cell Libraries.
327-332
Electronic Edition (ACM DL) BibTeX
- Donald G. Baltus, Thomas Varga, Robert C. Armstrong, John Duh, T. G. Matheson:
Developing a Concurrent Methodology for Standard-Cell Library Generation.
333-336
Electronic Edition (ACM DL) BibTeX
- John F. Croix, D. F. Wong:
A Fast And Accurate Technique To Optimize Characterization Tables For Logic Synthesis.
337-340
Electronic Edition (ACM DL) BibTeX
Modeling and Transformations in Synthesis
Statistical Power Estimation Techniques
Co-Simulation
Panel:
Challenges in Worldwide IP Reuse with Embedded Tutorial:
Applying VSIA Standards to System on Chip Design
Emerging Technologies and Architectures for Low Power
- Pankaj Pant, Vivek De, Abhijit Chatterjee:
Device-Circuit Optimization for Minimal Energy and Power Consumption in CMOS Random Logic Networks.
403-408
Electronic Edition (ACM DL) BibTeX
- James Kao, Anantha Chandrakasan, Dimitri Antoniadis:
Transistor Sizing Issues and Tool For Multi-Threshold CMOS Technology.
409-414
Electronic Edition (ACM DL) BibTeX
- Thucydides Xanthopoulos, Yoshifumi Yaoi, Anantha Chandrakasan:
Architectural Exploration Using Verilog-Based Power Estimation: A Case Study of the IDCT.
415-420
Electronic Edition (ACM DL) BibTeX
- Chi-Ying Tsui, Kai-Keung Chan, Qing Wu, Chih-Shun Ding, Massoud Pedram:
A Power Estimation Framework for Designing Low Power Portable Video Applications.
421-424
Electronic Edition (ACM DL) BibTeX
- Qi Wang, Sarma B. K. Vrudhula, Shantanu Ganguly:
An Investigation of Power Delay Trade-Offs on PowerPC Circuits.
425-428
Electronic Edition (ACM DL) BibTeX
High Level Synthesis for Low Power
Module Generation
BIST and DFT
- Douglas Chang, Mike Tien-Chien Lee, Malgorzata Marek-Sadowska, Takashi Aikyo, Kwang-Ting Cheng:
A Test Synthesis Approach to Reducing BALLAST DFT Overhead.
466-471
Electronic Edition (ACM DL) BibTeX
- Kun-Han Tsai, Sybille Hellebrand, Janusz Rajski, Malgorzata Marek-Sadowska:
STARBIST: Scan Autocorrelated Random Pattern Generation.
472-477
Electronic Edition (ACM DL) BibTeX
- Huan-Chih Tsai, Kwang-Ting Cheng, Chih-Jen Lin, Sudipta Bhawmik:
A Hybrid Algorithm for Test Point Selection for Scan-Based BIST.
478-483
Electronic Edition (ACM DL) BibTeX
Panel:
Hardware/Software Co-Verification
DSP & Telecommunication System Design
Embedded Tutorial:
High-Level Power Modeling,
Estimation,
and Optimization
Advances in Partitioning
Processor Test techniques
Panel:
The Next Generation HDL
Design Processes and Frameworks
Probabilistic Models of Input Data for Efficient Power Estimation
Hot Topics in Routing
Test Generation and Fault Simulation
Panel:
The Road Ahead in CPLD & FPGA Design Methodology
Deep Submicron Modeling and Analysis
Technology-Dependent Optimization for Performance and Power
- Jason Cong, Chang Wu:
FPGA Synthesis with Retiming and Pipelining for Clock Period Minimization of Sequential Circuits.
644-649
Electronic Edition (ACM DL) BibTeX
- Rajendran Panda, Farid N. Najm:
Technology-Dependent Transformations for Low-Power Synthesis.
650-655
Electronic Edition (ACM DL) BibTeX
- Chau-Shen Chen, TingTing Hwang, C. L. Liu:
Low Power FPGA Design - A Re-engineering Approach.
656-661
Electronic Edition (ACM DL) BibTeX
- Yi-Min Jiang, Angela Krstic, Kwang-Ting Cheng, Malgorzata Marek-Sadowska:
Post-Layout Logic Restructuring for Performance Optimization.
662-665
Electronic Edition (ACM DL) BibTeX
- Masako Murofushi, Takashi Ishioka, Masami Murakata, Takashi Mitsuhashi:
Layout Driven Re-synthesis for Low Power Consumption LSIs.
666-669
Electronic Edition (ACM DL) BibTeX
CAD Issues for Micro-Electro-Mechanical Systems
- William C. Tang:
Overview of Microelectromechanical Systems and Design Processes.
670-673
Electronic Edition (ACM DL) BibTeX
- Jean-Michel Karam, Bernard Courtois, Hicham Boutamine, P. Drake, András Poppe, Vladimir Székely, Márta Rencz, Klaus Hofmann, Manfred Glesner:
CAD and Foundries for Microsystems.
674-679
Electronic Edition (ACM DL) BibTeX
- Tamal Mukherjee, Gary K. Fedder:
Structured Design of Microelectromechanical Systems.
680-685
Electronic Edition (ACM DL) BibTeX
- Narayan R. Aluru, James White:
Algorithms for Coupled Domain MEMS Simulation.
686-690
Electronic Edition (ACM DL) BibTeX
Hardware/Software Partitioning
Embedded Tutorial:
Chip Parasitic Extraction and Signal Integrity Verification
Panel:
Noise and Signal Integrity in Deep Submicron Design
Designing High Performance and Low Power Microprocessors Using Full Custom Techniques
Formal Verification techniques
Placement Techniques
Panel:
The EDA Startup Experience:
Financing the Venture
Heterogeneous System Analysis
- Steven P. Levitan, Philippe J. Marchand, Timothy P. Kurzweg, M. A. Rempel, Donald M. Chiarulli, C. Fan, F. B. McCormick:
Computer-Aided Design of Free-Space Opto-Electronic Systems.
768-773
Electronic Edition (ACM DL) BibTeX
- Matthias Bauer, Wolfgang Ecker:
Hardware/Software Co-Simulation in a VHDL-Based Test Bench Approach.
774-779
Electronic Edition (ACM DL) BibTeX
- Clifford Liem, Marco Cornero, Miguel Santana, Pierre G. Paulin, Ahmed Amine Jerraya, Jean-Marc Gentit, Jean Lopez, Xavier Figari, Laurent Bergher:
Am Embedded System Case Study: The Firm Ware Development Environment for a Multimedia Audio Processor.
780-785
Electronic Edition (ACM DL) BibTeX
Copyright © Sat May 16 23:04:37 2009
by Michael Ley (ley@uni-trier.de)
