5th Asian Test Symposium (ATS '96), November 20-22, 1996, Hsinchu, Taiwan.
IEEE Computer Society 1996 BibTeX
@proceedings{DBLP:conf/ats/1996,
title = {5th Asian Test Symposium (ATS '96), November 20-22, 1996, Hsinchu,
Taiwan},
booktitle = {Asian Test Symposium},
publisher = {IEEE Computer Society},
year = {1996},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Keynote Speech
Test Pattern Generation
- Vishwani D. Agrawal, Michael L. Bushnell, Qing Lin:
Redundancy Identification Using Transitive Closure.
4-9
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- Hsing-Chung Liang, Chung-Len Lee, Jwu E. Chen:
Invalid State Identification for Sequential Circuit Test Generation.
10-15
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- Irith Pomeranz, Sudhakar M. Reddy:
On Test Generation for Interconnected Finite-State Machines: The Input Sequence Propagation Problem.
16-21
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- Dirk Stroobandt, Jan Van Campenhout:
Hierarchical Test Generation with Built-In Fault Diagnosis.
22-28
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- J. Th. van der Linden, M. H. Konijnenburg, A. J. van de Goor:
Circuit Partitioned Automatic Test Pattern Generation Constrained by Three-State Buses and Restrictors.
29-33
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- Michael Nicolaidis, Rubin A. Parekhji, M. Boudjit:
E-Groups: A New Technique for Fast Backward Propagation in System Level Test Generation.
34-41
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- Y.-M. Hur, J.-H. Shin, K.-H. Lee, Y.-S. Son, I.-C. Lim, Y.-H. Kim:
Efficient Path Delay Fault Test Generation Algorithms for Weighted Random Robust Testing.
42-
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Board and System-Level Test
- Wuudiann Ke:
Hybrid Pin Control Using Boundary-Scan And Its Applications.
44-49
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- Jin-Hua Hong, Chung-Hung Tsai, Cheng-Wen Wu:
Hierarchical Testing Using the IEEE Std 1149.5 Module Test and Maintenance Slave Interface Module.
50-55
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- Po-Ching Hsu, Sying-Jyan Wang:
Testing And Diagnosis Of Board Interconnects In Microprocessor-Based Systems.
56-61
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- Chauchin Su, Shyh-Shen Hwang, Shyh-Jye Jou, Yuan-Tzu Ting:
Syndrome Simulation And Syndrome Test For Unscanned Interconnects.
62-67
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- Hiroyuki Michinishi, Tokumi Yokohira, Takuji Okamoto, Tomoo Inoue, Hideo Fujiwara:
A Test Methodology for Interconnect Structures of LUT-based FPGAs.
68-74
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- Wang-Dauh Tseng, Kuochen Wang:
Testable Design and Testing of MCMs Based on Multifrequency Scan.
75-
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Design for Testability
- Yoshihiro Konno, Kazushi Nakamura, Tatsushige Bitoh, Koji Saga, Seiken Yano:
A Consistent Scan Design System for Large-Scale ASICs.
82-87
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- Toshinori Hosokawa, Kenichi Kawaguchi, Mitsuyasu Ohta, Michiaki Muraoka:
A Design for testability Method Using RTL Partitioning.
88-93
Electronic Edition (link) BibTeX
- Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita:
Partially Parallel Scan Chain for Test Length Reduction by Using Retiming Technique.
94-99
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- Kuen-Jong Lee, Jing-Jou Tang, Tsung-Chu Huang, Cheng-Liang Tsai:
Combination Of Automatic Test Pattern Generation And Built-In Intermediate Voltage Sensing For Detecting CMOS Bridging Faults.
100-
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Concurrent Error Detection and Fault Tolerance
Synthesis for Testability
- Tomoo Inoue, Toshimitsu Masuzawa, Hiroshi Youra, Hideo Fujiwara:
An Approach To The Synthesis Of Synchronizable Finite State Machines With Partial Scan.
130-135
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- Zhuxing Zhao, Zhongcheng Li, Yinghua Min:
Waveform Polynomial Manipulation Using Bdds.
136-141
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- Li-Ren Huang, Jing-Yang Jou, Sy-Yen Kuo, Wen-Bin Liao:
Easily Testable Data Path Allocation Using Input/Output Registers.
142-
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- Harry Hengster, Rolf Drechsler, Bernd Becker, Stefan Eckrich, Tonja Pfeiffer:
AND/EXOR based Synthesis of Testable KFDD-Circuits with Small Depth.
148-
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- Uwe Sparmann, H. Mueller, Sudhakar M. Reddy:
Minimal Delay Test Sets for Unate Gate Networks.
155-
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IDDQ and Fault Modeling
Keynote Speech
Circuit and System-Level Diagnostics
Industrial Applications
Practical Issues
- Cheng-Ping Wang, Chin-Long Wey:
Test Generation Of Analog Switched-Current Circuits.
276-281
Electronic Edition (link) BibTeX
- Vladimir Székely, Márta Rencz, Jean-Michel Karam, Marcelo Lubaszewski, Bernard Courtois:
Thermal Monitoring Of Safety-Critical Integrated Systems.
282-288
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- Xiaofan Yang, Tinghuai Chen, Zehan Cao, Zhongshi He, Hongqing Cao:
A New Scheme For The Fault Diagnosis Of Multiprocessor Systems.
289-294
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- Serge N. Demidenko, Vincenzo Piuri:
On-Line Testing In Digital Neural Networks.
295-
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Copyright © Sat May 16 22:59:03 2009
by Michael Ley (ley@uni-trier.de)
