10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan.
IEEE Computer Society 2001, ISBN 0-7695-1378-6 BibTeX
@proceedings{DBLP:conf/ats/2001,
title = {10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto,
Japan},
booktitle = {Asian Test Symposium},
publisher = {IEEE Computer Society},
year = {2001},
isbn = {0-7695-1378-6},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Keynote Address
Design for Testability
Fault Modeling for Memories
Diagnosis
ATPG
Embedded Memory Test
- Kuo-Liang Cheng, Chia-Ming Hsueh, Jing-Reng Huang, Jen-Chieh Yeh, Chih-Tsun Huang, Cheng-Wen Wu:
Automatic Generation of Memory Built-in Self-Test Cores for System-on-Chip.
91-96
Electronic Edition (link) BibTeX
- Davide Appello, Fulvio Corno, M. Giovinetto, Maurizio Rebaudengo, Matteo Sonza Reorda:
A P1500 Compliant BIST-Based Approach to Embedded RAM Diagnosis.
97-102
Electronic Edition (link) BibTeX
- Chih-Wea Wang, Ruey-Shing Tzeng, Chi-Feng Wu, Chih-Tsun Huang, Cheng-Wen Wu, Shi-Yu Huang, Shyh-Horng Lin, Hsin-Po Wang:
A Built-in Self-Test and Self-Diagnosis Scheme for Heterogeneous SRAM Clusters.
103-
Electronic Edition (link) BibTeX
IDDQ and Diagnosis Test
- Teppei Takeda, Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Yukiya Miura, Kozo Kinoshita:
IDDQ Sensing Technique for High Speed IDDQ Testing.
111-116
Electronic Edition (link) BibTeX
- Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Takeomi Tamesada:
CMOS Open Defect Detection Based on Supply Current in Time-Variable Electric Field and Supply Voltage Application.
117-122
Electronic Edition (link) BibTeX
- Iwao Yamazaki, Hiroki Yamanaka, Toshio Ikeda, Masahiro Takakura, Yasuo Sato:
An Approach to Improve the Resolution of Defect-Based Diagnosis.
123-
Electronic Edition (link) BibTeX
Test Compaction
Pattern Generation for Memory Test
- Mill-Jer Wang, R.-L. Jiang, J.-W. Hsia, Chih-Hu Wang, Jwu E. Chen:
Guardband Determination for the Detection of Off-State and Junction Leakages in DRAM Testing.
151-156
Electronic Edition (link) BibTeX
- Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto:
Memory Read Faults: Taxonomy and Automatic Test Generation.
157-163
Electronic Edition (link) BibTeX
- Serge N. Demidenko, A. J. van de Goor, S. Henderson, P. Knoppers:
Simulation and Development of Short Transparent Tests for RAM.
164-
Electronic Edition (link) BibTeX
Virtual Tester and Beam Testing
SoC Test Access Mechanism
RTL ATPG
Delay Test
SoC Test Scheduling
- Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch:
A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores.
253-258
Electronic Edition (link) BibTeX
- Erik Larsson, Zebo Peng:
Test Scheduling and Scan-Chain Division under Power Constraint.
259-264
Electronic Edition (link) BibTeX
- Yu Huang, Wu-Tung Cheng, Chien-Chung Tsai, Nilanjan Mukherjee, Omer Samman, Yahya Zaidan, Sudhakar M. Reddy:
Resource Allocation and Test Scheduling for Concurrent Test of Core-Based SoC D.
265-
Electronic Edition (link) BibTeX
FSM Test
Online Testing and Fault Injection line
- Emmanuel Simeu, Ahmad Abdelhay, Mohammad A. Naal:
Robust Self Concurrent Test of Linear Digital Systems.
293-298
Electronic Edition (link) BibTeX
- Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto, Luca Tagliaferri:
Control-Flow Checking via Regular Expressions.
299-303
Electronic Edition (link) BibTeX
- Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante:
FPGA-Based Fault Injection for Microprocessor Systems.
304-
Electronic Edition (link) BibTeX
Advances in BIST
- Ken-ichi Yamaguchi, Hiroki Wada, Toshimitsu Masuzawa, Hideo Fujiwara:
BIST Method Based on Concurrent Single-Control Testability of RTL Data Paths.
313-318
Electronic Edition (link) BibTeX
- Sobeeh Almukhaizim, Peter Petrov, Alex Orailoglu:
Faults in Processor Control Subsystems: Testing Correctness and Performance Faults in the Data Prefetching Unit.
319-324
Electronic Edition (link) BibTeX
- Bernd Könemann, Carl Barnhart, Brion L. Keller, Thomas J. Snethen, Owen Farnsworth, Donald L. Wheater:
A SmartBIST Variant with Guaranteed Encoding.
325-
Electronic Edition (link) BibTeX
Analog Test
Fault Tolerance
Various Ideas for BIST
- Ismet Bayraktaroglu, Alex Orailoglu:
Selecting a PRPG: Randomness, Primitiveness, or Sheer Luck?
373-378
Electronic Edition (link) BibTeX
- Kenichi Ichino, Takeshi Asakawa, Satoshi Fukumoto, Kazuhiko Iwasaki, Seiji Kajihara:
Hybrid BIST Using Partially Rotational Scan.
379-384
Electronic Edition (link) BibTeX
- Biplab K. Sikdar, Niloy Ganguly, Aniket Karmakar, Subha Sankar Chowdhury, Parimal Pal Chaudhuri:
Multiple Attractor Cellular Automata for Hierarchical Diagnosis of VLSI Circuits.
385-390
Electronic Edition (link) BibTeX
- Dongkyu Youn, Taehyung Kim, Sungju Park:
A Microcode-Based Memory BIST Implementing Modified March Algorithm.
391-395
Electronic Edition (link) BibTeX
- Hamed Farshbaf, Mina Zolfy, Shahrzad Mirkhani, Zainalabedin Navabi:
Fault Simulation for VHDL Based Test Bench and BIST Evaluation.
396-
Electronic Edition (link) BibTeX
Analog/Mixed Signal Test
Verification
DFT Application to Real Chips
- Yasuo Sato, M. Sato, K. Tsutsumida, Toyohito Ikeya, M. Kawashima:
A Practical Logic BIST for ASIC Designs.
457
Electronic Edition (link) BibTeX
- Tetsuo Kamada:
Tx7901 Dft.
458
Electronic Edition (link) BibTeX
- Toshinobu Ono, Akira Kozawa, Takashi Kimura, Yoshihiro Konno, Koji Saga:
An Application of Partial Scan Techniques to a High-End System LSI Design.
459
Electronic Edition (link) BibTeX
- Hisayoshi Hanai, Shinji Yamada, Hisaya Mori, Eisaku Yamashita, Teruhiko Funakura:
Built-out Self-Test (BOST) for Analog Circuits in a System LSI: Test Solution to Reduce Test Costs.
460
Electronic Edition (link) BibTeX
- M. Suzuki, R. Shimizu, N. Naka, K. Nakamura:
High-Speed Interface Testing.
461
Electronic Edition (link) BibTeX
- Tetsuji Kishi, Mitsuyasu Ohta, Takashi Taniguchi, Hiroshi Kadota:
A New Inter-Core Built-In-Self-Test Circuits for Tri-State Buffers in the System on a Chip.
462
Electronic Edition (link) BibTeX
- Xiaoqing Wen, Hsin-Po Wang:
A Flexible Logic BIST Scheme and Its Application to SoC Designs.
463
Electronic Edition (link) BibTeX
Practical Ideas from Universities
Copyright © Sat May 16 22:59:04 2009
by Michael Ley (ley@uni-trier.de)
