2008 |
12 | EE | Rupak Samanta,
Ganesh Venkataraman,
Nimay Shah,
Jiang Hu:
Elastic Timing Scheme for Energy-Efficient and Robust Performance.
ISQED 2008: 537-542 |
2007 |
11 | EE | Bao Liu,
Andrew B. Kahng,
Xu Xu,
Jiang Hu,
Ganesh Venkataraman:
A Global Minimum Clock Distribution Network Augmentation Algorithm for Guaranteed Clock Skew Yield.
ASP-DAC 2007: 24-31 |
10 | EE | Ganesh Venkataraman,
Jiang Hu:
A Placement Methodology for Robust Clocking.
VLSI Design 2007: 881-886 |
9 | EE | Ganesh Venkataraman,
Jiang Hu,
Frank Liu:
Integrated Placement and Skew Optimization for Rotary Clocking.
IEEE Trans. VLSI Syst. 15(2): 149-158 (2007) |
2006 |
8 | EE | Ganesh Venkataraman,
Jiang Hu,
Frank Liu,
Cliff C. N. Sze:
Integrated placement and skew optimization for rotary clocking.
DATE 2006: 756-761 |
7 | EE | Rupak Samanta,
Ganesh Venkataraman,
Jiang Hu:
Clock buffer polarity assignment for power noise reduction.
ICCAD 2006: 558-562 |
6 | EE | Ganesh Venkataraman,
Zhuo Feng,
Jiang Hu,
Peng Li:
Combinatorial algorithms for fast clock mesh optimization.
ICCAD 2006: 563-567 |
2005 |
5 | EE | Ganesh Venkataraman,
Cliff C. N. Sze,
Jiang Hu:
Skew scheduling and clock routing for improved tolerance to process variations.
ASP-DAC 2005: 594-599 |
4 | | Di Wu,
Ganesh Venkataraman,
Jiang Hu,
Quiyang Li,
Rabi N. Mahapatra:
DiCER: distributed and cost-effective redundancy for variation tolerance.
ICCAD 2005: 393-397 |
3 | | Ganesh Venkataraman,
Nikhil Jayakumar,
Jiang Hu,
Peng Li,
Sunil P. Khatri,
Anand Rajaram,
Patrick McGuinness,
Charles J. Alpert:
Practical techniques to reduce skew and its variations in buffered clock networks.
ICCAD 2005: 592-596 |
2004 |
2 | EE | Kasturi R. Varadarajan,
Ganesh Venkataraman:
Graph decomposition and a greedy algorithm for edge-disjoint paths.
SODA 2004: 379-380 |
2003 |
1 | EE | Ganesh Venkataraman,
Sudhakar M. Reddy,
Irith Pomeranz:
GALLOP: Genetic Algorithm based Low Power FSM Synthesis by Simultaneous Partitioning and State Assignment.
VLSI Design 2003: 533-538 |