IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 17

Volume 17, Number 1, January 1998

• Andrew B. Kahng, Majid Sarrafzadeh:
  Guest Editorial. 1-2
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• Charles J. Alpert, Tony F. Chan, Andrew B. Kahng, Igor L. Markov, Pep Mulet:
  Faster minimization of linear wirelength for global placement. 3-13
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• Jeffrey L. Burns, Jack A. Feldman:
  C5M-a control-logic layout synthesis system for high-performance microprocessors. 14-23
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• Jason Cong, Andrew B. Kahng, Kwok-Shing Leung:
  Efficient algorithms for the minimum shortest path Steiner arborescence problem with applications to VLSI physical design. 24-39
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• Rony Kay, Lawrence T. Pileggi:
  EWA: efficient wiring-sizing algorithm for signal nets and clock nets. 40-49
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• Huiqun Liu, Martin D. F. Wong:
  Network-flow-based multiway partitioning with area and pin constraints. 50-59
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• Hiroshi Murata, Kunihiro Fujiyoshi, Mineo Kaneko:
  VLSI/PCB placement with obstacles based on sequence pair. 60-68
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Volume 17, Number 2, February 1998

• Radu Marculescu, Diana Marculescu, Massoud Pedram:
  Probabilistic modeling of dependencies during switching activity analysis. 73-83
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• James E. Beck, Daniel P. Siewiorek:
  Automatic configuration of embedded multicomputer systems. 84-95
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• Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau:
  Incorporating DRAM access modes into high-level synthesis. 96-109
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• Lieven Vandenberghe, Stephen P. Boyd, Abbas A. El Gamal:
  Optimizing dominant time constant in RC circuits. 110-125
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• Parthasarathi Dasgupta, Susmita Sur-Kolay, Bhargab B. Bhattacharya:
  A unified approach to topology generation and optimal sizing of floorplans. 126-135
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• Kaiyuan Huang, Vinod K. Agarwal, Krishnaiyan Thulasiraman:
  Diagnosis of clustered faults and wafer testing. 136-148
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• Valery Axelrad:
  Grid quality and its influence on accuracy and convergence in device simulation. 149-157
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• Sujit Dey, Vijay Gangaram, Miodrag Potkonjak:
  A controller redesign technique to enhance testability of controller-data path circuits. 157-168
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• Steve H. Jen, Bing J. Sheu:
  A compact and unified MOS DC current model with highly continuous conductances for low-voltage ICs. 169-172
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• Harsha Sathyamurthy, Sachin S. Sapatnekar, John P. Fishburn:
  Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization. 173-182
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• Chia-Chun Tsai, Chwan-Ming Wang, Sao-Jie Chen:
  NEWS: a net-even-wiring system for the routing on a multilayer PGA package. 182-189
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Volume 17, Number 3, March 1998

• Thang Nguyen Bui, Byung Ro Moon:
  GRCA: a hybrid genetic algorithm for circuit ratio-cut partitioning. 193-204
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• Peter A. Beerel, Chris J. Myers, Teresa H. Y. Meng:
  Covering conditions and algorithms for the synthesis of speed-independent circuits. 205-219
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• Luca Benini, Enrico Macii, Massimo Poncino, Giovanni De Micheli:
  Telescopic units: a new paradigm for performance optimization of VLSI designs. 220-232
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• D. Michael Miller:
  An improved method for computing a generalized spectral coefficient. 233-238
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• Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel:
  Application of genetically engineered finite-state-machine sequences to sequential circuit ATPG. 239-254
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• David B. Lavo, Brian Chess, Tracy Larrabee, F. Joel Ferguson:
  Diagnosing realistic bridging faults with single stuck-at information. 255-268
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• Irith Pomeranz, Sudhakar M. Reddy:
  Low-complexity fault simulation under the multiple observation time and the restricted multiple observation time testing approaches. 269-278
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• José C. Monteiro, Srinivas Devadas, Abhijit Ghosh:
  Sequential logic optimization for low power using input-disabling precomputation architectures. 279-284
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Volume 17, Number 4, April 1998

• Daniel Brand, Reinaldo A. Bergamaschi, Leon Stok:
  Don't cares in synthesis: theoretical pitfalls and practical solutions. 285-304
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• Ali M. Niknejad, Ranjit Gharpurey, Robert G. Meyer:
  Numerically stable Green function for modeling and analysis of substrate coupling in integrated circuits. 305-315
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• Kai Zhu, Martin D. F. Wong:
  Switch bound allocation for maximizing routability in timing-driven routing of FPGA's. 316-323
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• Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal:
  The path-status graph with application to delay fault simulation. 324-332
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• Irith Pomeranz, Sudhakar M. Reddy:
  Design-for-testability for path delay faults in large combinational circuits using test points. 333-343
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• Alessandro Balboni, Claudio Costi, Massimo Pellencin, Andrea Quadrini, Donatella Sciuto:
  Clock skew reduction in ASIC logic design: a methodology for clock tree management. 344-356
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• David Ihsin Cheng, Kwang-Ting Cheng, Deborah C. Wang, Malgorzata Marek-Sadowska:
  A hybrid methodology for switching activities estimation. 357-366
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• M. K. Kidambi, Akhilesh Tyagi, Mohammed R. Madani, Magdy A. Bayoumi:
  Three-dimensional defect sensitivity modeling for open circuits in ULSI structures. 366-371
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• Suet Fong Tin, Ashraf A. Osman, Kartikeya Mayaram:
  Comments on "A small-signal MOSFET model for radio frequency IC applications". 372-374
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Volume 17, Number 5, May 1998

• Herman Schmit, Donald E. Thomas:
  Address generation for memories containing multiple arrays. 377-385
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• Mitrajit Chatterjee, Dhiraj K. Pradhan, Wolfgang Kunz:
  LOT: Logic Optimization with Testability. New transformations for logic synthesis. 386-399
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• Masaki Kondo, Hidetoshi Onodera, Keikichi Tamaru:
  Model-adaptable MOSFET parameter-extraction method using an intermediate model. 400-405
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• Hsiao-Feng Steven Chen, D. T. Lee:
  On crossing minimization problem. 406-418
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• Kerry S. Lowe, P. Glenn Gulak:
  A joint gate sizing and buffer insertion method for optimizing delay and power in CMOS and BiCMOS combinational logic. 419-434
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• Vladimir B. Dmitriev-Zdorov:
  Multicycle generalization. A new way to improve the convergence of waveform relaxation for circuit simulation. 435-443
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• John F. Beetem:
  Rebel: a clustering algorithm for look-up table FPGA's. 444-451
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• Krishnendu Chakrabarty:
  Zero-aliasing space compaction using linear compactors with bounded overhead. 452-457
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• Rolf Drechsler, Martin Sauerhoff, Detlef Sieling:
  The complexity of the inclusion operation on OFDD's. 457-459
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• Juho Kim, David Hung-Chang Du:
  Performance optimization by gate sizing and path sensitization. 459-462
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Volume 17, Number 6, June 1998

• Chih-Shun Ding, Qing Wu, Cheng-Ta Hsieh, Massoud Pedram:
  Stratified random sampling for power estimation. 465-471
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• Evguenii I. Goldberg, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
  Theory and algorithms for face hypercube embedding. 472-488
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• Peichen Pan, Arvind K. Karandikar, C. L. Liu:
  Optimal clock period clustering for sequential circuits with retiming. 489-498
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• Sudip Nag, Rob A. Rutenbar:
  Performance-driven simultaneous placement and routing for FPGA's. 499-518
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• Shigetoshi Nakatake, Kunihiro Fujiyoshi, Hiroshi Murata, Yoji Kajitani:
  Module packing based on the BSG-structure and IC layout applications. 519-530
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• Albrecht P. Stroele, Hans-Joachim Wunderlich:
  Hardware-optimal test register insertion. 531-539
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• Naveena Nagi, Abhijit Chatterjee, Heebyung Yoon, Jacob A. Abraham:
  Signature analysis for analog and mixed-signal circuit test response compaction. 540-546
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• Shangzhi Sun, David Hung-Chang Du, Hsi-Chuan Chen:
  Efficient timing analysis for CMOS circuits considering data dependent delays. 546-552
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Volume 17, Number 7, July 1998

• Koichi Fukuda, Kenji Nishi:
  An interpolated flux scheme for cellular automaton device simulation. 553-560
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• Ernst Leitner, Siegfried Selberherr:
  Mixed-element decomposition method for three-dimensional grid adaptation. 561-572
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• Harm Arts, Michel R. C. M. Berkelaar, Koen van Eijk:
  Computing observability don't cares efficiently through polarization. 573-581
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• Kevin J. Kerns, Andrew T. Yang:
  Preservation of passivity during RLC network reduction via split congruence transformations. 582-591
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• Daniel R. Brasen, Gabriele Saucier:
  Using cone structures for circuit partitioning into FPGA packages. 592-600
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• Stan Y. Liao, Srinivas Devadas, Kurt Keutzer:
  Code density optimization for embedded DSP processors using data compression techniques. 601-608
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• Michael Jünger, Sebastian Leipert, Petra Mutzel:
  A note on computing a maximal planar subgraph using PQ-trees. 609-612
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• Xiao Quan Li, Marwan A. Jabri:
  Machine learning-based VLSI cells shape function estimation. 613-623
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• A. R. Naseer, M. Balakrishnan, Anshul Kumar:
  Direct mapping of RTL structures onto LUT-based FPGA's. 624-631
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• Raymond S. Winton, William R. Bandy:
  A simple, continuous, analytical charge/capacitance model for the short-channel MOSFET. 631-638
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Volume 17, Number 8, August 1998

• Yuhua Cheng, Kai Chen, Kiyotaka Imai, Chenming Hu:
  A unified MOSFET channel charge model for device modeling in circuit simulation. 641-644
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• Altan Odabasioglu, Mustafa Celik, Lawrence T. Pileggi:
  PRIMA: passive reduced-order interconnect macromodeling algorithm. 645-654
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• Charles J. Alpert, Jen-Hsin Huang, Andrew B. Kahng:
  Multilevel circuit partitioning. 655-667
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• Yi-Kan Cheng, Prasun Raha, Chin-Chi Teng, Elyse Rosenbaum, Sung-Mo Kang:
  ILLIADS-T: an electrothermal timing simulator for temperature-sensitive reliability diagnosis of CMOS VLSI chips. 668-681
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• Kwang-Il Park, Kyu Ho Park:
  Event suppression by optimizing VHDL programs. 682-691
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• Chih-Ang Chen, Sandeep K. Gupta:
  Efficient BIST TPG design and test set compaction via input reduction. 692-705
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• Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha:
  A design-for-testability technique for register-transfer level circuits using control/data flow extraction. 706-723
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• Shih-Arn Hwang, Jin-Hua Hong, Cheng-Wen Wu:
  Sequential circuit fault simulation using logic emulation. 724-736
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Volume 17, Number 9, September 1998

• Jason Cong, Chang Wu:
  An efficient algorithm for performance-optimal FPGA technology mapping with retiming. 738-748
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• Alex Kondratyev, Michael Kishinevsky, Alexandre Yakovlev:
  Hazard-free implementation of speed-independent circuits. 749-771
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• Feng Wang, Donald L. Dietmeyer:
  Exploiting near symmetry in multilevel logic synthesis. 772-781
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• Kenneth Y. Yun, Bill Lin, David L. Dill, Srinivas Devadas:
  BDD-based synthesis of extended burst-mode controllers. 782-792
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• Jun Dong Cho, Majid Sarrafzadeh:
  Four-bend top-down global routing. 793-802
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• Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
  Maple-opt: a performance-oriented simultaneous technology mapping, placement, and global routing algorithm for FPGAs. 803-818
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• Asawaree Kalavade, P. A. Subrahmanyam:
  Hardware/software partitioning for multifunction systems. 819-837
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• Chih-Chang Lin, Malgorzata Marek-Sadowska, Kwang-Ting Cheng, Mike Tien-Chien Lee:
  Test-point insertion: scan paths through functional logic. 838-851
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• Chih-Chang Lin, Malgorzata Marek-Sadowska, Mike Tien-Chien Lee, Kuang-Chien Chen:
  Cost-free scan: a low-overhead scan path design. 852-861
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• Zhihua Wang, Georges G. E. Gielen, Willy M. C. Sansen:
  Probabilistic fault detection and the selection of measurements for analog integrated circuits. 862-872
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• Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal:
  A parallel-vector concurrent-fault simulator and generation of single-input-change tests for path-delay faults. 873-876
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• Yiming Gong, Sreejit Chakravarty:
  Locating bridging faults using dynamically computed stuck-at fault dictionaries. 876-887
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Volume 17, Number 10, October 1998

• Ali Dasdan, Rajesh K. Gupta:
  Faster maximum and minimum mean cycle algorithms for system-performance analysis. 889-899
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• Bharat P. Dave, Niraj K. Jha:
  COHRA: hardware-software cosynthesis of hierarchical heterogeneous distributed embedded systems. 900-919
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• Robert P. Dick, Niraj K. Jha:
  MOGAC: a multiobjective genetic algorithm for hardware-software cosynthesis of distributed embedded systems. 920-935
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• Miodrag Potkonjak, Mani B. Srivastava:
  Behavioral optimization using the manipulation of timing constraints. 936-947
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• Luca Benini, Patrick Vuillod, Giovanni De Micheli:
  Iterative remapping for logic circuits. 948-964
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• Rolf Drechsler, Bernd Becker:
  Ordered Kronecker functional decision diagrams-a data structure for representation and manipulation of Boolean functions. 965-973
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• Taewhan Kim, William Jao, Steven W. K. Tjiang:
  Circuit optimization using carry-save-adder cells. 974-984
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• Michael D. Hutton, Jonathan Rose, Jerry P. Grossman, Derek G. Corneil:
  Characterization and parameterized generation of synthetic combinational benchmark circuits. 985-996
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• Ramachandra Achar, Michel S. Nakhla, Qi-Jun Zhang:
  Full-wave analysis of high-speed interconnects using complex frequency hopping. 997-1016
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• Irith Pomeranz, Sudhakar M. Reddy:
  Test sequences to achieve high defect coverage for synchronous sequential circuits. 1017-1029
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• Jing-Jou Tang, Kuen-Jong Lee, Bin-Da Liu:
  A graph representation for programmable logic arrays to facilitate testing and logic design. 1030-1043
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• Krishnendu Chakrabarty, Brian T. Murray:
  Design of built-in test generator circuits using width compression. 1044-1051
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• Vivek Tiwari, Sharad Malik, Pranav Ashar:
  Guarded evaluation: pushing power management to logic synthesis/design. 1051-1060
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Volume 17, Number 11, November 1998

• Enrico Macii, Massoud Pedram, Fabio Somenzi:
  High-level power modeling, estimation, and optimization. 1061-1079
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• Cheng-Ta Hsieh, Massoud Pedram:
  Microprocessor power estimation using profile-driven program synthesis. 1080-1089
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• S. Turgis, Daniel Auvergne:
  A novel macromodel for power estimation in CMOS structures. 1090-1098
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• Chih-Shun Ding, Chi-Ying Tsui, Massoud Pedram:
  Gate-level power estimation using tagged probabilistic simulation. 1099-1107
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• Enric Pastor, Jordi Cortadella, Alex Kondratyev, Oriol Roig:
  Structural methods for the synthesis of speed-independent circuits. 1108-1129
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• Michael Theobald, Steven M. Nowick:
  Fast heuristic and exact algorithms for two-level hazard-free logic minimization. 1130-1147
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• Rui Martins, Wolfgang Pyka, Rainer Sabelka, Siegfried Selberherr:
  High-precision interconnect analysis. 1148-1159
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• Mahesh B. Patil:
  New discretization scheme for two-dimensional semiconductor device simulation on triangular grid. 1160-1165
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• Chris C. N. Chu, Martin D. F. Wong:
  A matrix synthesis approach to thermal placement. 1166-1174
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• Hannah Honghua Yang, Martin D. F. Wong:
  Optimal min-area min-cut replication in partitioned circuits. 1175-1183
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• Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alexander Saldanha, Alexander Taubin:
  Partial-scan delay fault testing of asynchronous circuits. 1184-1199
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• Haluk Konuk, F. Joel Ferguson:
  Oscillation and sequential behavior caused by opens in the routing in digital CMOS circuits. 1200-1210
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• Radomir S. Stankovic:
  Some remarks on terminology in spectral techniques for logic design: Walsh transform and Hadamard matrices. 1211-1214
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Volume 17, Number 12, December 1998

• Edward A. Lee, Alberto L. Sangiovanni-Vincentelli:
  A framework for comparing models of computation. 1217-1229
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• Carl J. Wordelman, Thomas J. T. Kwan, Charles M. Snell:
  Comparison of statistical enhancement methods for Monte Carlo semiconductor simulation. 1230-1235
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• Walter Bohmayr, Alexander Burenkov, Jürgen Lorenz, Heiner Ryssel, Siegfried Selberherr:
  Monte Carlo simulation of silicon amorphization during ion implantation. 1236-1243
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• Richard Plasun, Michael Stockinger, Siegfried Selberherr:
  Integrated optimization capabilities in the VISTA technology CAD framework. 1244-1251
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• M. B. Anand, Hideki Shibata, Masakazu Kakumu:
  Multiobjective optimization of VLSI interconnect parameters. 1252-1261
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• Akira Nagao, Isao Shirakawa, Takashi Kambe:
  A layout approach to monolithic microwave IC. 1262-1272
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• Aurobindo Dasgupta, Ramesh Karri:
  High-reliability, low-energy microarchitecture synthesis. 1273-1280
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• Chi-Ying Tsui, Massoud Pedram, Alvin M. Despain:
  Low-power state assignment targeting two- and multilevel logic implementations. 1281-1291
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• Andrew R. Conn, Paula K. Coulman, Ruud A. Haring, Gregory L. Morrill, Chandramouli Visweswariah, Chai Wah Wu:
  JiffyTune: circuit optimization using time-domain sensitivities. 1292-1309
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• Jacob Savir:
  Random pattern testability of memory address logic. 1310-1318
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• Pierre-Yves Calland, Anne Mignotte, Olivier Peyran, Yves Robert, Frédéric Vivien:
  Retiming DAGs [direct acyclic graph]. 1319-1325
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• Vinay Dabholkar, Sreejit Chakravarty, Irith Pomeranz, Sudhakar M. Reddy:
  Techniques for minimizing power dissipation in scan and combinational circuits during test application. 1325-1333
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• Aiguo Xie, Peter A. Beerel:
  Efficient state classification of finite-state Markov chains. 1334-1339
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