9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan.
IEEE Computer Society 2000, ISBN 0-7695-0887-1 BibTeX
@proceedings{DBLP:conf/ats/2000,
title = {9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei,
Taiwan},
booktitle = {Asian Test Symposium},
publisher = {IEEE Computer Society},
year = {2000},
isbn = {0-7695-0887-1},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Keynote Address I
Keynote Address II
Industry Session I:
CAD Tools on Testing
Industry Session II:
Taiwan Test Industry:
Value Added Testing in the New Millennium
Panel I
Panel II
Analog & Mixed Signal Test I
Memory Built-in Self-Test and Self-Diagnosis
- Chih-Wea Wang, Chi-Feng Wu, Jin-Fu Li, Cheng-Wen Wu, Tony Teng, Kevin Chiu, Hsiao-Ping Lin:
A built-in self-test and self-diagnosis scheme for embedded SRAM.
45-50
Electronic Edition (link) BibTeX
- Jing-Reng Huang, Chee-Kian Ong, Kwang-Ting Cheng, Cheng-Wen Wu:
An FPGA-based re-configurable functional tester for memory chips.
51-57
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- Chen-Huan Chiang, Sandeep K. Gupta:
BIST TPG for SRAM cluster interconnect testing at board level.
58-65
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- Sying-Jyan Wang, Chen-Jung Wei:
Efficient built-in self-test algorithm for memory.
66-
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Analog & Mixed Signal Test II
- Wooyoung Choi, Ramesh Harjani, Bapiraju Vinnakota:
Optimal test-set generation for parametric fault detection in switched capacitor filters.
72-77
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- Luigi Carro, Érika F. Cota, Marcelo Lubaszewski, Yves Bertrand, Florence Azaïs, Michel Renovell:
TI-BIST: a temperature independent analog BIST for switched-capacitor filters.
78-83
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- Matthew Worsman, Mike W. T. Wong, Y. S. Lee:
Analog circuit equivalent faults in the D.C. domain.
84-89
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- Yin-Chao Huang, Chung-Len Lee, Jun-Weir Lin, Jwu E. Chen, Chauchin Su:
A methodology for fault model development for hierarchical linear systems.
90-95
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- José Vicente Calvano, Vladimir Castro Alves, Marcelo Lubaszewski:
Testing a PWM circuit using functional fault models and compact test vectors for operational amplifiers.
96-
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Fault Simulation & Timing Simulation
- Liang-Chi Chen, Sandeep K. Gupta, Melvin A. Breuer:
A new framework for static timing analysis, incremental timing refinement, and timing simulation.
102-107
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- Irith Pomeranz, Sudhakar M. Reddy:
On the feasibility of fault simulation using partial circuit descriptions.
108-113
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- Susmita Sur-Kolay, Marly Roncken, Ken S. Stevens, Parimal Pal Chaudhuri, Rob Roy:
Fsimac: a fault simulator for asynchronous sequential circuits.
114-119
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- Arabi Keshk, Yukiya Miura, Kozo Kinoshita:
Simulation of resistive bridging fault to minimize the presence of intermediate voltage and oscillation in CMOS circuits.
120-124
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- Stanislav Polonsky, Moyra K. McManus, Daniel R. Knebel, Steve Steen, Pia Sanda:
Non-invasive timing analysis of IBM G6 microprocessor L1 cache using picosecond imaging circuit analysis.
125-
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Fault Analysis I
- Said Hamdioui, A. J. van de Goor:
An experimental analysis of spot defects in SRAMs: realistic fault models and tests.
131-138
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- Seiji Kajihara, Takashi Shimono, Irith Pomeranz, Sudhakar M. Reddy:
Enhanced untestable path analysis using edge graphs.
139-144
Electronic Edition (link) BibTeX
- Lijian Li, Xiaoyang Yu, Cheng-Wen Wu, Yinghua Min:
A waveform simulator based on Boolean process.
145-150
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- Jennifer Dworak, Michael R. Grimaila, Brad Cobb, Ting-Chi Wang, Li-C. Wang, M. Ray Mercer:
On the superiority of DO-RE-ME/MPG-D over stuck-at-based defective part level prediction.
151-
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Test Generation I
Functional Testing
Built-in Self-Test I
Software Testing & Test Synthesis
Embedded-Core Testing
Memory Testing
Test Generation II
- Wei-Yu Chen, Sandeep K. Gupta, Melvin A. Breuer:
Test generation for crosstalk-induced faults: framework and computational result.
305-310
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- Bin Liu, Fabrizio Lombardi, Wei-Kang Huang:
Testing programmable interconnect systems: an algorithmic approach.
311-316
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- Irith Pomeranz, Sudhakar M. Reddy:
Reducing test application time for full scan circuits by the addition of transfer sequences.
317-322
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- Michel Renovell, Jean Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian:
TOF: a tool for test pattern generation optimization of an FPGA application oriented test.
323-328
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- Y. Morihiro, T. Toneda:
Formal verification of data-path circuits based on symbolic simulation.
329-
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IDDQ Testing
- Chih-Wen Lu, Chauchin Su, Chung-Len Lee, Jwu E. Chen:
Is IDDQ testing not applicable for deep submicron VLSI in year 2011?
338-343
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- Masaki Hashizume, Hiroyuki Yotsuyanagi, Masahiro Ichimiya, Takeomi Tamesada, Masashi Takeda:
High speed IDDQ test and its testability for process variation.
344-349
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- Toshiyuki Maeda, Kozo Kinoshita:
Memory reduction of I/sub DDQ/ test compaction for internal and external bridging faults.
350-355
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- Yann Antonioli, Tsuneo Inufushi, Shigeki Nishikawa, Kozo Kinoshita:
A high-speed IDDQ sensor implementation.
356-361
Electronic Edition (link) BibTeX
- Tsuyoshi Shinogi, Masahiro Ushio, Terumine Hayashi:
Cyclic greedy generation method for limited number of IDDQ tests.
362-
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Built-in Self-Test II
Testability Analysis and Design for Testability
Fault Tolerance
Fault Analysis II
Low-Power Testing
Self-Checking Circuits and Concurrent Fault Detection
Tutorial 1
Tutorial 2
Copyright © Sat May 16 22:59:04 2009
by Michael Ley (ley@uni-trier.de)
