14. VLSI Design 2001:
Bangalore,
India
14th International Conference on VLSI Design (VLSI Design 2001), 3-7 January 2001, Bangalore, India.
IEEE Computer Society 2001, ISBN 0-7695-0831-6 BibTeX
Tutorials
- Noel Menezes, Sachin S. Sapatnekar:
Optimization and Analysis Techniques for the Deep Submicron Regime.
3-4 BibTeX
- Doris Keitel-Schulz, Norbert Wehn, Francky Catthoor, Preeti Ranjan Panda:
Embedded Memories in System Design: Technology, Application, Design and Tools.
5-6 BibTeX
- Sudipta Bhawmik:
ntroduction to SystemC.
7-8 BibTeX
- Anand Raghunathan, Sujit Dey:
Low-Power Mobile Wireless Communication System Design: Protocols, Architectures, and Design Methodologies.
9-10 BibTeX
- Ruchira Kamdar, Seetharam Gundurao, Rajiv V. Joshi, N. S. Murty:
IBM's Blue Logic Design Methodology-Circuits and Physical Design.
11-12 BibTeX
- Deepak Kataria:
Next Generation Network Processors.
13-15 BibTeX
- Mahesh Mehendale, Santhosh Kumar Amanna:
Functional Verification of Programmable DSP Cores.
16-17 BibTeX
- V. Ranganatha, R. Sunda:
System Level Testability Issues of Core Based System-on-a-Chip.
18 BibTeX
- Ramesh Harjani, Jackson Harvey:
Tutorial: CMOS Analog Circuits for Wireless Communications.
18 BibTeX
Embedded Systems I
- Anupam Rastogi, M. Balakrishnan, Anshul Kumar:
Integrating Communication Cost Estimation in Embedded Systems Design : A PCI Case Study.
23-28
Electronic Edition (link) BibTeX
- Kanishka Lahiri, Sujit Dey, Anand Raghunathan:
Evaluation of the Traffic-Performance Characteristics of System-on-Chip Communication Architectures.
29-35
Electronic Edition (link) BibTeX
- Ajit Gupte, Mahesh Mehendale, Ramesh Ramamritham, Deepa Nair:
Performance Considerations in Embedded DSP based System-On-a-Chip Designs.
36-41
Electronic Edition (link) BibTeX
- Abhijit K. Deb, Ahmed Hemani, Johnny Öberg, Adam Postula, Dan Lindqvist:
Hardware Software Codesign of DSP System Using Grammar Based Approach.
42-47
Electronic Edition (link) BibTeX
- Koen Danckaert, Chidamber Kulkarni, Francky Catthoor, Hugo De Man, Vivek Tiwari:
A Systematic Approach for System Bus Load Reduction Applied to Medical Imaging.
48-
Electronic Edition (link) BibTeX
Embedded Systems II
- Debashis Panigrahi, Sujit Dey, Ramesh R. Rao, Kanishka Lahiri, Carla-Fabiana Chiasserini, Anand Raghunathan:
Battery Life Estimation of Mobile Embedded Systems.
57-63
Electronic Edition (link) BibTeX
- Pavan Kumar, Mani B. Srivastava:
Power-aware Multimedia Systems using Run-time Prediction.
64-69
Electronic Edition (link) BibTeX
- Prabhat Mishra, Peter Grun, Nikil D. Dutt, Alexandru Nicolau:
Processor-Memory Co-Exploration driven by a Memory-Aware Architecture Description Language.
70-75
Electronic Edition (link) BibTeX
- Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar:
ASIP Design Methodologies : Survey and Issues.
76-
Electronic Edition (link) BibTeX
SOC Methodologies
Test I
- Ruifeng Guo, Irith Pomeranz, Sudhakar M. Reddy:
On Improving Static Test Compaction for Sequential Circuits.
111-116
Electronic Edition (link) BibTeX
- Sitaram Yadavalli, Sandip Kundu:
On Fault-Simulation Through Embedded Memories On Large Industrial Designs.
117-121
Electronic Edition (link) BibTeX
- Debabrata Bagchi, Dipanwita Roy Chowdhury, Joy Mukherjee, Santanu Chattopadhyay:
A Novel Strategy to Test Core Based Designs.
122-127
Electronic Edition (link) BibTeX
- Debesh Kumar Das, Bhargab B. Bhattacharya, Satoshi Ohtake, Hideo Fujiwara:
Testable Design of Sequential Circuits with Improved Fault Efficiency.
128-133
Electronic Edition (link) BibTeX
- Sameer Sharma, Michael S. Hsiao:
Combination of Structural and State Analysis for Partial Scan.
134-
Electronic Edition (link) BibTeX
Test II
Verification
Low-Power I
- Rex Min, Manish Bhardwaj, Seong-Hwan Cho, Eugene Shih, Amit Sinha, Alice Wang, Anantha Chandrakasan:
Low-Power Wireless Sensor Networks.
205-210
Electronic Edition (link) BibTeX
- Hendrawan Soeleman, Kaushik Roy, Bipul Chandra Paul:
Sub-Domino Logic: Ultra-Low Power Dynamic Sub-Threshold Digital Logic.
211-214
Electronic Edition (link) BibTeX
- Ashok K. Murugavel, N. Ranganathan, Ramamurti Chandramouli, Srinath Chavali:
Average Power in Digital CMOS Circuits using Least Square Estimation.
215-220
Electronic Edition (link) BibTeX
- Amit Sinha, Anantha Chandrakasan:
Dynamic Voltage Scheduling Using Adaptive Filtering of Workload Traces.
221-226
Electronic Edition (link) BibTeX
- Nikhil Tripathi, Amit M. Bhosle, Debasis Samanta, Ajit Pal:
Optimal Assignment of High Threshold Voltage for Synthesizing Dual Threshold CMOS Circuits.
227-
Electronic Edition (link) BibTeX
Low-Power II
Analog Design
FPGA
- K. Yan:
Logic Synthesis for CPLDs and FPGAs with PLA-Style Logic Blocks.
291-298
Electronic Edition (link) BibTeX
- Malay Haldar, Anshuman Nayak, Alok N. Choudhary, Prithviraj Banerjee, U. Nagaraj Shenoy:
Fpga Hardware Synthesis From Matlab.
299-304
Electronic Edition (link) BibTeX
- U. Nagaraj Shenoy, Prithviraj Banerjee, Alok N. Choudhary, Mahmut T. Kandemir:
Efficient Synthesis of Array Intensive Computations onto FPGA Based Accelerators.
305-310
Electronic Edition (link) BibTeX
- Wolfgang Günther, Rolf Drechsler:
Performance Driven Optimization for MUX based FPGAs.
311-316
Electronic Edition (link) BibTeX
- Sujatha Sundararaman, Sriram Govindarajan, Ranga Vemuri:
Application Specific Macro Based Synthesis.
317-
Electronic Edition (link) BibTeX
Physical Design I
Physical Design II
Built-In Test
- Der-Cheng Huang, Wen-Ben Jone, Sunil R. Das:
An Efficient Parallel Transparent Bist Method For Multiple Embedded Memory Buffers.
379-384
Electronic Edition (link) BibTeX
- Dilip K. Bhavsar, Rishan Tan:
Observability Register Architecture For Efficient Production Test And Debug Of Vlsi Circuits.
385-390
Electronic Edition (link) BibTeX
- Thomas Clouqueur, Ozen Ercevik, Kewal K. Saluja, Hiroshi Takahashi:
Efficient Signature-Based Fault Diagnosis Using Variable Size Windows.
391-396
Electronic Edition (link) BibTeX
- Der-Cheng Huang, Wen-Ben Jone, Sunil R. Das:
A Parallel Built-In Self-Diagnostic Method For Embedded Memory Buffers.
397-402
Electronic Edition (link) BibTeX
- Biplab K. Sikdar, Purnabha Majumder, Monalisa Mukherjee, Parimal Pal Chaudhuri, Debesh K. Das, Niloy Ganguly:
Hierarchical Cellular Automata As An On-Chip Test Pattern Generator.
403-
Electronic Edition (link) BibTeX
Synthesis
Architecture
- Masa-Aki Fukase, Ryusuke Egawa, Tomoaki Sato, Tadao Nakamura:
Scaling Up Of Wave Pipelines.
439-445
Electronic Edition (link) BibTeX
- Alexander Worm, Holger Lamm, Norbert Wehn:
Vlsi Architectures For High-Speed Map Decoders.
446-453
Electronic Edition (link) BibTeX
- Biplab K. Sikdar, Purnabha Majumder, Parimal Pal Chaudhuri, Niloy Ganguly:
Design Of Multiple Attractor Gf (2p) Cellular AutomataFor Diagnosis Of Vlsi Circuits.
454-459
Electronic Edition (link) BibTeX
- Ram Lakhan Gupta, Anshul Kumar, Aalbert Van Der Werf, Natalino G. Busa:
Synthesizing A Long Latency Unit Within Vliw Processor.
460-
Electronic Edition (link) BibTeX
Technology I
- Omkaram Nalamasu, Pat G. Watson, Raymond A. Cirelli, Jeff Bude, Isik C. Kizilyalli, Ross A. Kohler:
Invited Paper: Extending Resolution Limits of IC Fabrication Technology: Demonstration by Device Fabrication and Circuit Performance.
469-469 BibTeX
- Mayukh Bhattacharya, Pinaki Mazumder, Ronald J. Lomax:
Fd-Tlm Electromagnetic Field Simulation Of High-Speed Iii-V Heterojunction Bipolar Transistor Digital Logic Gates.
470-474
Electronic Edition (link) BibTeX
- G. Shrivastav, S. Mahapatra, V. Ramgopal Rao, J. Vasi, K. G. Anil, C. Fink, Walter Hansch, I. Eisele:
erformance Optimization Of 60 Nm Channel Length Vertical Mosfets Using Channel Engineering.
475-478
Electronic Edition (link) BibTeX
- Nihar R. Mohapatra, A. Dutta, Madhav P. Desai, V. Ramgopal Rao:
Effect Of Fringing Capacitances In Sub 100 Nm Mosfet's With High-K Gate Dielectrics.
479-
Electronic Edition (link) BibTeX
Technology II
Deep Sub-Micron
- Dinesh Pamunuwa, Hannu Tenhunen:
Repeater Insertion To Minimise Delay In Coupled Interconnects.
513-517
Electronic Edition (link) BibTeX
- N. V. Arvind, P. R. Suresh, V. Sivakumar, Chandrani Pal, Debaprasad Das:
Integrated Crosstalk And Oxide Integrity Analysis In Dsm Designs.
518-523
Electronic Edition (link) BibTeX
- Marco Delaurenti, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, Maurizio Zamboni:
Switching Noise Analysis Framework For High Speed Logic Families.
524-530
Electronic Edition (link) BibTeX
- V. Sankara Subramanian, C. P. Ravikumar:
Estimating Crosstalk From Vlsi Layouts.
531-
Electronic Edition (link) BibTeX
Copyright © Sat May 16 23:46:43 2009
by Michael Ley (ley@uni-trier.de)
