ISQED 2005:
San Jose,
California,
USA
6th International Symposium on Quality of Electronic Design (ISQED 2005), 21-23 March 2005, San Jose, CA, USA.
IEEE Computer Society 2005, ISBN 0-7695-2301-3 BibTeX
Tutorial I
Tutorial II
Session EP1- Panel
Plenary Session 1P
Session 1A:
Tools and Flows for Quality Design
- Aaron N. Ng, Igor L. Markov:
Toward Quality EDA Tools and Tool Flows Through High-Performance Computing.
22-27
Electronic Edition (link) BibTeX
- Alex Gyure, Alireza Kasnavi, Sam C. Lo, Peivand F. Tehrani, William Shu, Mahmoud Shahram, Joddy W. Wang, Jindrich Zejda:
Noise Library Characterization for Large Capacity Static Noise Analysis Tools.
28-34
Electronic Edition (link) BibTeX
- Qianying Tang, Jianwen Zhu:
Two-Dimensional Layout Migration by Soft Constraint Satisfaction.
35-39
Electronic Edition (link) BibTeX
- Luo Chun, Yang Jun, Shi Longxing, Wu XuFan, Zhang Yu:
Domain Strategy and Coverage Metric for Validation.
40-45
Electronic Edition (link) BibTeX
Session 1B:
High Level Power/Noise Reduction Techniques
- Dongku Kang, Yiran Chen, Kaushik Roy:
Power Supply Noise-Aware Scheduling and Allocation for DSP Synthesis.
48-53
Electronic Edition (link) BibTeX
- Shivakumar Swaminathan, Sanjay B. Patel, James Dieffenderfer, Joel Silberman:
Reducing Power Consumption during TLB Lookups in a PowerPC Embedded Processor.
54-58
Electronic Edition (link) BibTeX
- Kee-Jong Kim, Chris H. Kim, Kaushik Roy:
TFT-LCD Application Specific Low Power SRAM Using Charge-Recycling Technique.
59-64
Electronic Edition (link) BibTeX
- David Roberts, Todd M. Austin, David Blaauw, Trevor N. Mudge, Krisztián Flautner:
Error Analysis for the Support of Robust Voltage Scaling.
65-70
Electronic Edition (link) BibTeX
Session 1C:
Leakage and Dynamic Power Issues
- Bhavana Jharia, Sankar Sarkar, R. P. Agarwal:
Analytical Study of Impact Ionization and Subthreshold Current in Submicron n-MOSFET.
72-76
Electronic Edition (link) BibTeX
- Afshin Abdollahi, Farzan Fallah, Massoud Pedram:
Analysis and Optimization of Static Power Considering Transition Dependency of Leakage Current in VLSI Circuits.
77-82
Electronic Edition (link) BibTeX
- Jayakumaran Sivagnaname, Hung C. Ngo, Kevin J. Nowka, Robert K. Montoye, Richard B. Brown:
Controlled-Load Limited Switch Dynamic Logic Circuit.
83-87
Electronic Edition (link) BibTeX
- Harmander Deogun, Rahul M. Rao, Dennis Sylvester, Richard B. Brown, Kevin J. Nowka:
Dynamically Pulsed MTCMOS with Bus Encoding for Total Power and Crosstalk Minimization.
88-93
Electronic Edition (link) BibTeX
Session 1D:
Poster Session
- Jin He, Jane Xi, Mansun Chan, Hui Wan, Mohan V. Dunga, Babak Heydari, Ali M. Niknejad, Chenming Hu:
Charge-Based Core and the Model Architecture of BSIM5.
96-101
Electronic Edition (link) BibTeX
- Lionel Riviere-Cazaux, Kevin Lucas, Jon Fitch:
Integration Of Design For Manufacturability (DFM) Practices In Design Flows.
102-106
Electronic Edition (link) BibTeX
- Carlo Roma, Pierluigi Daglio, Guido De Sandre, Marco Pasotti, Marco Poles:
How Circuit Analysis and Yield Optimization Can Be Used To Detect Circuit Limitations Before Silicon Results.
107-112
Electronic Edition (link) BibTeX
- Mini Nanua, David Blaauw, Chanhee Oh:
Leakage Current Modeling in PD SOI Circuits.
113-117
Electronic Edition (link) BibTeX
- Jasjeet Kaur:
A Balanced Scorecard for Systemic Quality in Electronic Design Automation: An Implementation Method for an EDA Company.
118-122
Electronic Edition (link) BibTeX
- Arun Shrimali, Anand Venkitachalam, Ravi Arora:
Issues and Challenges in Ramp to Production.
123-127
Electronic Edition (link) BibTeX
- C. K. Tang, Parag K. Lala, James Patrick Parkerson:
A Technique for Designing Totally Self-Checking Domino Logic Circuits.
128-132
Electronic Edition (link) BibTeX
- C. Talarico, B. Pillilli, K. L. Vakati, J. M. Wang:
Early Assessment of Leakage Power for System Level Design.
133-136
Electronic Edition (link) BibTeX
- Zhaojun Wo, Israel Koren:
Technology Mapping for Reliability Enhancement in Logic Synthesis.
137-142
Electronic Edition (link) BibTeX
- DiaaEldin Khalil, Mohamed Dessouky, Vincent Bourguet, Marie-Minerve Louërat, Andreia Cathelin, Hani Ragai:
Evaluation of Capacitor Ratios in Automated Accurate Common-Centroid Capacitor Arrays.
143-147
Electronic Edition (link) BibTeX
- Behnam Amelifard, Farzan Fallah, Massoud Pedram:
Closing the Gap between Carry Select Adder and Ripple Carry Adder: A New Class Closing the Gap between Carry Select Adder and Ripple Carry Adder: A New Class of Low-Power High-Performance Adders.
148-152
Electronic Edition (link) BibTeX
- Atsushi Kurokawa, Masaharu Yamamoto, Nobuto Ono, Tetsuro Kage, Yasuaki Inoue, Hiroo Masuda:
Capacitance and Yield Evaluations Using a 90-nm Process Technology Based on the Dense Power-Ground Interconnect Architecture.
153-158
Electronic Edition (link) BibTeX
- Haixia Gao, Yintang Yang, Xiaohua Ma, Gang Dong:
Testing for Resistive Shorts in FPGA Interconnects.
159-163
Electronic Edition (link) BibTeX
- Ewa Sokolowska, M. Barszcz, Bozena Kaminska:
TED Thermo Electrical Designer: A New Physical Design Verification Tool.
164-168
Electronic Edition (link) BibTeX
- Yong-Chan Ban, Soo-Han Choi, Ki-Hung Lee, Dong-Hyun Kim, Ji-Suk Hong, Yoo-Hyon Kim, Moon-Hyun Yoo, Jeong-Taek Kong:
A Fast Lithography Verification Framework for Litho-Friendly Layout Design.
169-174
Electronic Edition (link) BibTeX
- Harmander Deogun, Dennis Sylvester, David Blaauw:
Gate-Level Mitigation Techniques for Neutron-Induced Soft Error Rate.
175-180
Electronic Edition (link) BibTeX
- Hua Xiang, Kai-Yuan Chao, Martin D. F. Wong:
Exact Algorithms for Coupling Capacitance Minimization by Adding One Metal Layer.
181-186
Electronic Edition (link) BibTeX
- J. Huynh, B. Ngo, M. Pham, Lili He:
Design of a 10-bit TSMC 0.25um CMOS Digital to Analog Converter.
187-192
Electronic Edition (link) BibTeX
- R. Castagnetti, R. Venkatraman, B. Bartz, C. Monzel, T. Briscoe, Andres Teene, S. Ramesh:
A High-Performance SRAM Technology With Reduced Chip-Level Routing Congestion for SoC.
193-196
Electronic Edition (link) BibTeX
- Khadija Stewart, Themistoklis Haniotakis, Spyros Tragoudas:
Design and Evaluation of a Security Scheme for Sensor Networks.
197-201
Electronic Edition (link) BibTeX
- M. Welling, Spyros Tragoudas, Haibo Wang:
A Minimum Cut Based Re-Synthesis Approach.
202-207
Electronic Edition (link) BibTeX
- Young-Seok Hong, Heeseok Lee, Joon-Ho Choi, Moon-Hyun Yoo, Jeong-Taek Kong:
Analysis for Complex Power Distribution Networks Considering Densely Populated Vias.
208-212
Electronic Edition (link) BibTeX
- Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng:
Buffer Planning Algorithm Based on Partial Clustered Floorplanning.
213-219
Electronic Edition (link) BibTeX
ISQED Luncheon Speech
Session 2A:
Test Application and Cost Reduction
- Emmanouil Kalligeros, D. Kaseridis, Xrysovalantis Kavousianos, Dimitris Nikolos:
Reseeding-Based Test Set Embedding with Reduced Test Sequences.
226-231
Electronic Edition (link) BibTeX
- Themistoklis Haniotakis, Spyros Tragoudas, G. Pani:
Reduced Test Application Time Based on Reachability Analysis.
232-237
Electronic Edition (link) BibTeX
- Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li:
Using MUXs Network to Hide Bunches of Scan Chains.
238-243
Electronic Edition (link) BibTeX
- Ahmad A. Al-Yamani, Edward J. McCluskey:
BIST-Guided ATPG.
244-249
Electronic Edition (link) BibTeX
- Irith Pomeranz, Sudhakar M. Reddy:
Dynamic Test Compaction for Bridging Faults.
250-255
Electronic Edition (link) BibTeX
Session 2B:
DFM and Physical Layout
Session 2C:
Performance and Reliability Analysis for Yield Optimization
- Rahul M. Rao, Kanak Agarwal, Anirudh Devgan, Kevin J. Nowka, Dennis Sylvester, Richard B. Brown:
Parametric Yield Analysis and Constrained-Based Supply Voltage Optimization.
284-290
Electronic Edition (link) BibTeX
- Dipanjan Sengupta, Resve A. Saleh:
Power-Delay Metrics Revisited for 90nm CMOS Technology.
291-296
Electronic Edition (link) BibTeX
- Justin Gregg, Tom W. Chen:
Optimization of Individual Well Adaptive Body Biasing (IWABB) Using a Multiple Objective Evolutionary Algorithm.
297-302
Electronic Edition (link) BibTeX
- Syed M. Alam, Frank L. Wei, Chee Lip Gan, Carl V. Thompson, Donald E. Troxel:
Electromigration Reliability Comparison of Cu and Al Interconnects.
303-308
Electronic Edition (link) BibTeX
Session 3A:
Functional Verification and Test Generation
- Anat Dahan, Daniel Geist, Leonid Gluhovsky, Dmitry Pidan, Gil Shapir, Yaron Wolfsthal, Lyes Benalycherif, Romain Kamdem, Younes Lahbib:
Combining System Level Modeling with Assertion Based Verification.
310-315
Electronic Edition (link) BibTeX
- Haihua Yan, Gefu Xu, Adit D. Singh:
Low Voltage Test in Place of Fast Clock in DDSI Delay Test.
316-320
Electronic Edition (link) BibTeX
- Nicola Bombieri, Franco Fummi, Graziano Pravadelli:
Functional Verification of Networked Embedded Systems.
321-326
Electronic Edition (link) BibTeX
- Maria K. Michael, Stelios Neophytou, Spyros Tragoudas:
Functions for Quality Transition Fault Tests.
327-332
Electronic Edition (link) BibTeX
Session 3B:
Power Delivery and Distribution
Session 3C:
Quality System Level Design and Synthesis
- Animesh Datta, Swarup Bhunia, Nilanjan Banerjee, Kaushik Roy:
A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks.
358-363
Electronic Edition (link) BibTeX
- Suleyman Tosun, Ozcan Ozturk, Nazanin Mansouri, Ercument Arvas, Mahmut T. Kandemir, Yuan Xie, Wei-Lun Hung:
An ILP Formulation for Reliability-Oriented High-Level Synthesis.
364-369
Electronic Edition (link) BibTeX
- Haixia Gao, Yintang Yang, Xiaohua Ma, Gang Dong:
Analysis of the Effect of LUT Size on FPGA Area and Delay Using Theoretical Derivations.
370-374
Electronic Edition (link) BibTeX
- Suleyman Tosun, Nazanin Mansouri, Ercument Arvas, Mahmut T. Kandemir, Yuan Xie, Wei-Lun Hung:
Reliability-Centric Hardware/Software Co-Design.
375-380
Electronic Edition (link) BibTeX
Session 4A:
DFM for Circuit Design
- Xiaojun Li, Bing Huang, J. Qin, X. Zhang, Michael Talmor, Z. Gur, Joseph B. Bernstein:
Deep Submicron CMOS Integrated Circuit Reliability Simulation with SPICE.
382-389
Electronic Edition (link) BibTeX
- Henry H. Y. Chan, Zeljko Zilic:
Modeling Layout Effects for Sensitivity-Based Analog Circuit Optimization.
390-395
Electronic Edition (link) BibTeX
- Kambiz Rahimi, Chris Diorio:
In-Circuit Self-Tuning of Clock Latencies.
396-401
Electronic Edition (link) BibTeX
- Masanori Hashimoto, Tomonori Yamamoto, Hidetoshi Onodera:
Statistical Analysis of Clock Skew Variation in H-Tree Structure.
402-407
Electronic Edition (link) BibTeX
Session 4B:
Leakage and Reliability Management
- Saibal Mukhopadhyay, Keunwoo Kim, Jae-Joon Kim, Shih-Hsien Lo, Rajiv V. Joshi, Ching-Te Chuang, Kaushik Roy:
Modeling and Analysis of Gate Leakage in Ultra-thin Oxide Sub-50nm Double Gate Devices and Circuits.
410-415
Electronic Edition (link) BibTeX
- Ananth Somayaji Goda, Gautam Kapila:
Design For Degradation : CAD Tools for Managing Transistor Degradation Mechanisms.
416-420
Electronic Edition (link) BibTeX
- Puneet Gupta, Andrew B. Kahng, Puneet Sharma:
A Practical Transistor-Level Dual Threshold Voltage Assignment Methodology.
421-426
Electronic Edition (link) BibTeX
- Oleg Semenov, H. Sarbishaei, Manoj Sachdev:
Analysis and Design of LVTSCR-based EOS/ESD Protection Circuits for Burn-in Environment.
427-432
Electronic Edition (link) BibTeX
Session 4C:
Analog Test and BIST
Session EP2
Plenary Session 2P
Session 5A:
Design Methods and Tools in DSM
Session 5B:
Design Techniques for Leakage Reduction
Session 5C:
Variability Issues in Nanoscale Circuits
- Norman G. Gunther, Emad Hamadeh, Darrell Niemann, Iliya Pesic, Mahmud Rahman:
Modeling Intrinsic Fluctuations in Decananometer MOS Modeling Intrinsic Fluctuations in Decananometer MOS.
510-515
Electronic Edition (link) BibTeX
- Paul Friedberg, Yu Cao, Jason Cain, Ruth Wang, Jan M. Rabaey, Costas J. Spanos:
Modeling Within-Die Spatial Correlation Effects for Process-Design Co-Optimization.
516-521
Electronic Edition (link) BibTeX
- Vishak Venkatraman, Wayne Burleson:
Robust Multi-Level Current-Mode On-Chip Interconnect Signaling in the Presence of Process Variations.
522-527
Electronic Edition (link) BibTeX
Session 6A:
Issues in Noise and Timing
- Sreeram Chandrasekar, Gaurav Kumar Varshney, V. Visvanathan:
A Comprehensive Methodology for Noise Characterization of ASIC Cell Libraries.
530-535
Electronic Edition (link) BibTeX
- Shahin Nazarian, Massoud Pedram, Emre Tuncer, Tao Lin:
Sensitivity-Based Gate Delay Propagation in Static Timing Analysis.
536-541
Electronic Edition (link) BibTeX
- Zhenyu Qi, Hang Li, Sheldon X.-D. Tan, Lifeng Wu, Yici Cai, Xianlong Hong:
Fast Decap Allocation Algorithm For Robust On-Chip Power Delivery.
542-547
Electronic Edition (link) BibTeX
- Deepak C. Sekar:
Clock trees: differential or single ended?.
548-553
Electronic Edition (link) BibTeX
Session 6B:
Design Approaches for System in Package (SiP)
Session 6C:
DSM Interconnect Issues
- Muzhou Shao, Youxin Gao, Li-Pen Yuan, Hung-Ming Chen, Martin D. F. Wong:
Current Calculation on VLSI Signal Interconnects.
580-585
Electronic Edition (link) BibTeX
- Atsushi Kurokawa, Toshiki Kanamoto, Tetsuya Ibe, Akira Kasebe, Wei Fong Chang, Tetsuro Kage, Yasuaki Inoue, Hiroo Masuda:
Dummy Filling Methods for Reducing Interconnect Capacitance and Number of Fills.
586-591
Electronic Edition (link) BibTeX
- Vinita V. Deodhar, Jeffrey A. Davis:
Voltage Scaling, Wire Sizing and Repeater Insertion Design Rules for Wave-Pipelined VLSI Global Interconnect Circuits.
592-597
Electronic Edition (link) BibTeX
- Jiaxing Sun, Yun Zheng, Qing Ye, Tianchun Ye:
Interconnect Delay and Slew Metrics Using the First Three Moments.
598-602
Electronic Edition (link) BibTeX
- Pu Liu, Zhenyu Qi, Sheldon X.-D. Tan:
Passive Hierarchical Model Order Reduction and Realization of RLCM Circuits.
603-608
Electronic Edition (link) BibTeX
Session 7A:
Advances in Floor Planning
- Meng-Chiou Wu, Rung-Bin Lin:
Reticle Floorplanning and Wafer Dicing for Multiple Project Wafers.
610-615
Electronic Edition (link) BibTeX
- Jingyu Xu, Xianlong Hong, Tong Jing, Yang Yang:
Obstacle-Avoiding Rectilinear Minimum-Delay Steiner Tree Construction towards IP-Block-Based SOC Design.
616-621
Electronic Edition (link) BibTeX
- Hua Xiang, I-Min Liu, Martin D. F. Wong:
Wire Planning with Bounded Over-the-Block Wires.
622-627
Electronic Edition (link) BibTeX
- Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng:
Floorplanning with Consideration of White Space Resource Distribution for Repeater Planning.
628-633
Electronic Edition (link) BibTeX
- Wei-Lun Hung, Yuan Xie, Narayanan Vijaykrishnan, Charles Addo-Quaye, Theo Theocharides, Mary Jane Irwin:
Thermal-Aware Floorplanning Using Genetic Algorithms.
634-639
Electronic Edition (link) BibTeX
Session 7B:
Issues in On-Chip Communication and Analog/RF Designs
Session 7C:
Robust Design under Parameter Variations
- Dinesh Patil, Sunghee Yun, Seung-Jean Kim, Alvin Cheung, Mark Horowitz, Stephen P. Boyd:
A New Method for Design of Robust Digital Circuits.
676-681
Electronic Edition (link) BibTeX
- Hao Yu, Lei He:
Staggered Twisted-Bundle Interconnect for Crosstalk and Delay Reduction.
682-687
Electronic Edition (link) BibTeX
- Wei Ling, Yvon Savaria:
Analysis of Wave-Pipelined Domino Logic Circuit and Clocking Styles Subject to Parametric Variations.
688-693
Electronic Edition (link) BibTeX
- Andres Teene, Bob Davis, R. Castagnetti, J. Brown, S. Ramesh:
Impact of Interconnect Process Variations on Memory Performance and Design.
694-699
Electronic Edition (link) BibTeX
Copyright © Sat May 16 23:26:16 2009
by Michael Ley (ley@uni-trier.de)
