ITC 1994:
Washington,
DC,
USA
Proceedings IEEE International Test Conference 1994, TEST: The Next 25 Years, Washington, DC, USA, October 2-6, 1994.
IEEE Computer Society 1994, ISBN 0-7803-2103-0 BibTeX
@proceedings{DBLP:conf/itc/1994,
title = {Proceedings IEEE International Test Conference 1994, TEST: The
Next 25 Years, Washington, DC, USA, October 2-6, 1994},
publisher = {IEEE Computer Society},
year = {1994},
isbn = {0-7803-2103-0},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Session 1:
Plenary
Invited Address
Keynote Address
Invited Address
- Walt Wilson:
Faster, Better, Cheaper: What Does This Mean For The Test Industry?
13 BibTeX
Session 2:
Known-Good-Die Impact on MCM Testing
Session 3:
Microprocessor Test
- Dilip K. Bhavsar, John H. Edmondson:
Testability Strategy of the ALPHA AXP 21164 Microprocessor.
50-59 BibTeX
- Alfred L. Crouch, Matthew Pressly, Joe Circello:
Testabilty Features of the MC 68060 Microprocessor.
60-69 BibTeX
- Kalon Holdbrook, Sunil Joshi, Samir Mitra, Joe Petolino, Renu Raman, Michelle Wong:
microSPARCTM: A Case Study of Scan-Based Debug.
70-75 BibTeX
- Craig Hunter, E. Kofi Vida-Torku, Johnny LeBlanc:
Balancing Structured and Ad-hoc Design for Test: Testing of the PowerPC 603TM Microprocessor.
76-83 BibTeX
Session 4:
Test Strategy and the Bottom Line
Session 5:
Structured Methodologies for System Test
Session 6:
Delay Testing and Synthesis
Session 7:
Paving the Superhighway to Ultimate CMOS IC Quality
Session 8:
Sequential Test Generation
Session 9:
ATE Topics
Session 10:
System-Level Applications of BIST,
Boundary-Scan,
DFT
Session 11:
DFT by Clock Manipulation
Session 13 - Panel:
Testing High-Speed DRAMs
Session 14 - Panel:
Benchmarking Test Tools:
Are They Necessary and Why
Session 15 - Panel:
MCM Testing:
Is It Board Test or IC Test?
Session 17:
Applications of Memory BIST
Session 18:
Test Strategies for CMOS ICs
Session 19:
MCM Test Strategies
Session 20:
Test Engineering Accuracy
Session 21:
Hardware Pattern Generation and Compression
Session 22:
Practical Memory Testing
Session 23:
The Test Engineer's Role in...
... IC Test
- William R. Kosar:
Detection and Correction of Systematic Type 1 Test Errors Through Concurrent Engineering.
531-538 BibTeX
... Board Test
... System Test
Session 24:
Defect,
Quality,
and Cost Concerns for CMOS ICs
Session 25:
Software Environments for ATE
Session 26:
Real Fault Simulation for Real Circuits
Session 27:
Design for Test Considerations for Mixed-Signal Devices
Session 28:
Boundary Scan Design Techniques
Session 29:
ATE PIN Electronics,
Timing,
and Accuracy
Session 30:
Towards Quantifying Defect Coverage
Session 31:
New Test Technique Developments for Mixed Signal Devices
Session 32:
Test Data Systems,
Teams,
and Results
Session 33:
Effective Board-Level Test Vector Generation
Session 34:
Software Testing Tools
Session 35:
Memory Test Algorithms
Session 36:
DFT in Practice
Session 37:
Board Test Opportunities and Solutions
Session 38:
Innovation in Logic BIST
Session 39:
High-Level Test Generation
Session 40:
Test-Synthesis Practices
Session 41 - Panel:
Testers and Testing in the Next Ten Years
Session 43 - Panel:
Which Backplane Test Interfaces Should I Use?
Session 44 - Panel:
Boundary Scan:
It Is Time To Go beyond Its Boundaries
Copyright © Sat May 16 23:26:41 2009
by Michael Ley (ley@uni-trier.de)