14th Asian Test Symposium (ATS 2005), 18-21 December 2005, Calcutta, India.
IEEE Computer Society 2005, ISBN 0-7695-2481-8 BibTeX
Cover
Introduction
Tutorials
Plenary Talk
Banquet Speeches
Invited Talks
Session A1:
Analog and RF Testing:
I
- Donghoon Han, Abhijit Chatterjee:
Robust Built-In Test of RF ICs Using Envelope Detectors.
2-7
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- Haihua Yan, Adit D. Singh, Gefu Xu:
Delay Defect Characterization Using Low Voltage Test.
8-13
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- Shalabh Goyal, Michael Purtell:
Alternate Test Methodology for High Speed A/D Converter Testing on Low Cost Tester.
14-17
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- Junichi Hirase, Yoshiyuki Goi, Yoshiyuki Tanaka:
IDDQ Testing Method using a Scan Pattern for Production Testing.
18-21
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- Ajoy Kumar Palit, Lei Wu, Kishore K. Duganapalli, Walter Anheier, Jürgen Schlöffel:
A New, Flexible and Very Accurate Crosstalk Fault Model to Analyze the Effects of Coupling Noise between the Interconnects on Signal Integrity Losses in Deep Submicron Chips.
22-27
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Session B1:
Verification,
On-line and Software Testing
Session A2:
Analog and RF Testing:
II
Session B2:
Self-Checking,
On-line and Software Testing
- Daniel Marienfeld, Egor S. Sogomonyan, Vitalij Ocheretnij, Michael Gössel:
New Self-checking Output-Duplicated Booth Multiplier with High Fault Coverage for Soft Errors.
76-81
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- Guangyan Huang, Guangmei Zhang, Xiaowei Li, Yunzhan Gong:
A State Machine for Detecting C/C++ Memory Faults.
82-87
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- S. Biswas, P. Srikanth, R. Jha, S. Mukhopadhyay, A. Patra, D. Sarkar:
On-Line Testing of Digital Circuits for n-Detect and Bridging Fault Models.
88-93
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- Philip Samuel, Rajib Mall:
Boundary Value Testing based on UML Models.
94-99
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Session A3:
Interconnect Testing
Session B3:
BIST
Session A4:
SoC Testing
- Tomokazu Yoneda, Hisakazu Takakuwa, Hideo Fujiwara:
Power-Constrained Area and Time Co-Optimization for SoCs Based on Consecutive Testability.
150-155
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- Hiroyuki Nakamura, Akio Shirokane, Yoshihito Nishizaki, Anis Uzzaman, Vivek Chickermane, Brion L. Keller, Tsutomu Ube, Yoshihiko Terauchi:
Low Cost Delay Testing of Nanometer SoCs Using On-Chip Clocking and Test Compression.
156-161
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- Anders Larsson, Erik Larsson, Petru Eles, Zebo Peng:
SOC Test Scheduling with Test Set Sharing and Broadcasting.
162-169
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Session B4:
Yield Enhancement
- Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Kaushik Roy:
A Statistical Approach to Area-Constrained Yield Enhancement for Pipelined Circuits under Parameter Variations.
170-175
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- Saibal Mukhopadhyay, Arijit Raychowdhury, Hamid Mahmoodi-Meimand, Kaushik Roy:
Leakage Current Based Stabilization Scheme for Robust Sense-Amplifier Design for Yield Enhancement in Nano-scale SRAM.
176-181
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- Yu-Chun Dawn, Jen-Chieh Yeh, Cheng-Wen Wu, Chia-Ching Wang, Yung-Chen Lin, Chao-Hsun Chen:
Flash Memory Die Sort by a Sample Classification Method.
182-187
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- Junichi Hirase, Tatsuya Furukawa:
Chip Identification using the Characteristic Dispersion of Transistor.
188-193
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Session A5:
Delay and Defect-Based Testing
- Manan Syal, Michael S. Hsiao, Suriyaprakash Natarajan, Sreejit Chakravarty:
Untestable Multi-Cycle Path Delay Faults in Industrial Designs.
194-201
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- Narendra Devta-Prasanna, Sudhakar M. Reddy, Arun Gunda, P. Krishnamurthy, Irith Pomeranz:
Improved Delay Fault Coverage Using Subsets of Flip-flops to Launch Transitions.
202-207
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- I-De Huang, Sandeep K. Gupta:
Selection of Paths for Delay Testing.
208-215
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- Kohei Miyase, Kenta Terashima, Seiji Kajihara, Xiaoqing Wen, Sudhakar M. Reddy:
On Improving Defect Coverage of Stuck-at Fault Tests.
216-223
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Session B5:
Low Power Testing
- Shih Ping Lin, Chung-Len Lee, Jwu E. Chen:
A Scan Matrix Design for Low Power Scan-Based Test.
224-229
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- Youbean Kim, Myung-Hoon Yang, Yong Lee, Sungho Kang:
A New Low Power Test Pattern Generator using a Transition Monitoring Window based on BIST Architecture.
230-235
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- Hadi Esmaeilzadeh, Saeed Shamshiri, Pooya Saeedi, Zainalabedin Navabi:
ISC: Reconfigurable Scan-Cell Architecture for Low Power Testing.
236-241
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- Mohammed ElShoukry, Mohammad Tehranipoor, C. P. Ravikumar:
Partial Gating Optimization for Power Reduction During Test Application.
242-247
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Session A6:
Diagnosis,
Delay,
and Defect-Based Testing
- Wei Zou, Wu-Tung Cheng, Sudhakar M. Reddy:
Bridge Defect Diagnosis with Physical Information.
248-253
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- Yuki Yoshikaw, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara:
Design for Testability Based on Single-Port-Change Delay Testing for Data Paths.
254-259
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- Thomas Clouqueur, Hideo Fujiwara, Kewal K. Saluja:
A Class of Linear Space Compactors for Enhanced Diagnostic.
260-265
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- Sandip Kundu, Piet Engelke, Ilia Polian, Bernd Becker:
On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing.
266-271
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Session B6:
Test Generation and Fault Simulation
- Dong Hyun Baik, Kewal K. Saluja:
State-reuse Test Generation for Progressive Random Access Scan: Solution to Test Power, Application Time and Data Size.
272-277
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- Shahrzad Mirkhani, Zainalabedin Navabi:
Enhancing Fault Simulation Performance by Dynamic Fault Clustering.
278-283
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- Sukanta Das, Hafizur Rahaman, Biplab K. Sikdar:
Cost Optimal Design of Nonlinear CA based PRPG for Test Applications.
284-287
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- Hideyuki Ichihara, Tomoo Inoue, Naoki Okamoto, Toshinori Hosokawa, Hideo Fujiwara:
An Effective Design for Hierarchical Test Generation Based on Strong Testability.
288-293
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- Vishwani D. Agrawal, Alok S. Doshi:
Concurrent Test Generation.
294-299
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Session A7:
Design for Testability
Session B7:
Test Compression and Compaction
Session A8:
Design for Testability:
II
- Debdeep Mukhopadhyay, Shibaji Banerjee, Dipanwita Roy Chowdhury, Bhargab B. Bhattacharya:
CryptoScan: A Secured Scan Chain Architecture.
348-353
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- Shiyi Xu:
Pseudo-Parity Testing with Testable Design.
354-359
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- Katherine Shu-Min Li, Chung-Len Lee, Tagin Jiang, Chauchin Su, Jwu E. Chen:
Finite State Machine Synthesis for At-Speed Oscillation Testability.
360-365
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- Tsuyoshi Shinogi, Hiroyuki Yamada, Terumine Hayashi, Shinji Tsuruoka, Tomohiro Yoshikawa:
A Test Cost Reduction Method by Test Response and Test Vector Overlapping for Full-Scan Test Architecture.
366-371
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Session B8:
Test Compression,
Test Compaction,
and Defect-Based Testing
- Yinhe Han, Xiaowei Li, Shivakumar Swaminathan, Yu Hu, Anshuman Chandra:
Scan Data Volume Reduction Using Periodically Alterable MUXs Decompressor.
372-377
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- Aiman H. El-Maleh, S. Saqib Khursheed, Sadiq M. Sait:
Efficient Static Compaction Techniques for Sequential Circuits Based on Reverse Order Restoration and Test Relaxation.
378-385
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- Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, Shinji Kimura:
Low Power Test Compression Technique for Designs with Multiple Scan Chain.
386-389
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- Zhigang Jiang, Sandeep K. Gupta:
Threshold testing: Covering bridging and other realistic faults.
390-397
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Session A9:
Design for Testability:
III
Session B9:
Fault Modeling,
Processor Testing,
and Memory Testing
- Ilia Polian, Thomas Fiehn, Bernd Becker, John P. Hayes:
A Family of Logical Fault Models for Reversible Circuits.
422-427
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- Kedarnath J. Balakrishnan, Nur A. Touba, Srinivas Patil:
Compressing Functional Tests for Microprocessors.
428-433
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- Zaid Al-Ars, Said Hamdioui, Jörg E. Vollrath:
Investigations of Faulty DRAM Behavior Using Electrical Simulation Versus an Analytical Approach.
434-439
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- Ji-Xue Xiao, Guang-Ju Chen, Yong-Le Xie:
Arithmetic Test Strategy for FFT Processor.
440-443
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- Kazuko Kambe, Michiko Inoue, Hideo Fujiwara, Tsuyoshi Iwagaki:
Efficient Constraint Extraction for Template-Based Processor Self-Test Generation.
444-449
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Industry Session
Session C1:
SoC Test Practices
Session C2:
Defect-Based Testing
Session C4:
Advances in Test Generation and Verification
Session C5:
Test Data Compression and System Level Testing
Session C6:
Mixed Signal Testing
Session C7:
Delay Testing and Burn-in Test Methodologies
Copyright © Sat May 16 22:59:05 2009
by Michael Ley (ley@uni-trier.de)
