VTS 2007:
Berkeley,
CA,
USA
25th IEEE VLSI Test Symposium (VTS 2007), 6-10 May 2007, Berkeley, California, USA.
IEEE Computer Society 2007 BibTeX
RF Test I
Delay Test Quality
Memory Test
- O. Ginez, Jean Michel Daga, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
Retention and Reliability Problems in Embedded Flash Memories: Analysis and Test of Defective 2T-FLOTOX Tunnel Window.
47-52
Electronic Edition (link) BibTeX
- Yu-Tsao Hsing, Chun-Chieh Huang, Jen-Chieh Yeh, Cheng-Wen Wu:
SDRAM Delay Fault Modeling and Performance Testing.
53-58
Electronic Edition (link) BibTeX
- Zaid Al-Ars, Said Hamdioui, Georgi Gaydadjiev:
Optimizing Test Length for Soft Faults in DRAM Devices.
59-66
Electronic Edition (link) BibTeX
Test Compression
- Peter Wohl, John A. Waicukauski, Rohit Kapur, S. Ramnath, Emil Gizdarski, Thomas W. Williams, P. Jaini:
Minimizing the Impact of Scan Compression.
67-74
Electronic Edition (link) BibTeX
- Dariusz Czysz, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer:
Low Power Embedded Deterministic Test.
75-83
Electronic Edition (link) BibTeX
- Anshuman Chandra, Haihua Yan, Rohit Kapur:
Multimode Illinois Scan Architecture for Test Application Time and Test Data Volume Reduction.
84-92
Electronic Edition (link) BibTeX
Going after Defects
Online Test
Diagnosis I
- Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman, Maurice Lousberg, Ananta K. Majhi:
Diagnosis of Bridging Defects Based on Current Signatures at Low Power Supply Voltages.
145-150
Electronic Edition (link) BibTeX
- Jyun-Wei Chen, Ying-Yen Chen, Jing-Jia Liou:
Handling Pattern-Dependent Delay Faults in Diagnosis.
151-157
Electronic Edition (link) BibTeX
- Rosa Rodríguez-Montañés, Daniel Arumí, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman, Maurice Lousberg, Ananta K. Majhi:
Diagnosis of Full Open Defects in Interconnecting Lines.
158-166
Electronic Edition (link) BibTeX
ATPG for Delay Faults
- V. R. Devanathan, C. P. Ravikumar, V. Kamakoti:
Glitch-Aware Pattern Generation and Optimization Framework for Power-Safe Scan Test.
167-172
Electronic Edition (link) BibTeX
- Vikram Iyengar, Kenneth Pichamuthu, Andrew Ferko, Frank Woytowich, David E. Lackey, Gary Grise, Mark Taylor, Mike Degregorio, Steven F. Oakland:
An Integrated Framework for At-Speed and ATE-Driven Delay Test of Contract-Manufactured ASICs.
173-178
Electronic Edition (link) BibTeX
- Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram:
Supply Voltage Noise Aware ATPG for Transition Delay Faults.
179-186
Electronic Edition (link) BibTeX
Advances in Test
Diagnosis II
- Rajsekhar Adapa, Spyros Tragoudas, Maria K. Michael:
Accelerating Diagnosis via Dominance Relations between Sets of Faults.
219-224
Electronic Edition (link) BibTeX
- Wei Zou, Wu-Tung Cheng, Sudhakar M. Reddy, Huaxing Tang:
Speeding Up Effect-Cause Defect Diagnosis Using a Small Dictionary.
225-230
Electronic Edition (link) BibTeX
- Vishnu C. Vimjam, Enamul Amyeen, Ruifeng Guo, Srikanth Venkataraman, Michael S. Hsiao, Kai Yang:
Using Scan-Dump Values to Improve Functional-Diagnosis Methodology.
231-238
Electronic Edition (link) BibTeX
Failure Estimation
- Mohammad Hosseinabady, Mohammad Hossein Neishaburi, Pejman Lotfi-Kamran, Zainalabedin Navabi:
A UML Based System Level Failure Rate Assessment Technique for SoC Designs.
243-248
Electronic Edition (link) BibTeX
- John P. Hayes, Ilia Polian, Bernd Becker:
An Analysis Framework for Transient-Error Tolerance.
249-255
Electronic Edition (link) BibTeX
- Brian Mullins, Hossein Asadi, Mehdi Baradaran Tahoori, David R. Kaeli, Kevin Granlund, Rudy Bauer, Scott Romano:
Case Study: Soft Error Rate Analysis in Storage Systems.
256-264
Electronic Edition (link) BibTeX
Fault Prediction & Evaluation
- Chris Schuermyer, Jewel Pangilinan, Jay Jahangiri, Martin Keim, Janusz Rajski, Brady Benware:
Silicon Evaluation of Static Alternative Fault Models.
265-270
Electronic Edition (link) BibTeX
- Simon Wilson, Ben Flood, Suresh Goyal, Jim Mosher, Susan Bergin, Joseph O'Brien, Robert Kennedy:
Parameter Estimation for a Model with Both Imperfect Test and Repair.
271-276
Electronic Edition (link) BibTeX
- Mridul Agarwal, Bipul C. Paul, Ming Zhang, Subhasish Mitra:
Circuit Failure Prediction and Its Application to Transistor Aging.
277-286
Electronic Edition (link) BibTeX
Analog Test
High Level Test Techniques
Memory Repair
- Avijit Dutta, Nur A. Touba:
Multiple Bit Upset Tolerant Memory Using a Selective Cycle Avoidance Based SEC-DED-DAEC Code.
349-354
Electronic Edition (link) BibTeX
- Tsu-Wei Tseng, Chun-Hsien Wu, Yu-Jen Huang, Jin-Fu Li, Alex Pao, Kevin Chiu, Eliot Chen:
A Built-In Self-Repair Scheme for Multiport RAMs.
355-360
Electronic Edition (link) BibTeX
- A. Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian:
Un-Restored Destructive Write Faults Due to Resistive-Open Defects in the Write Driver of SRAMs.
361-368
Electronic Edition (link) BibTeX
SOC Test
- Thomas Edison Yu, Tomokazu Yoneda, Danella Zhao, Hideo Fujiwara:
Using Domain Partitioning in Wrapper Design for IP Cores Under Power Constraints.
369-374
Electronic Edition (link) BibTeX
- Jaehoon Song, Piljae Min, Hyunbean Yi, Sungju Park:
Design of Test Access Mechanism for AMBA-Based System-on-a-Chip.
375-380
Electronic Edition (link) BibTeX
- Tomokazu Yoneda, Akiko Shuto, Hideyuki Ichihara, Tomoo Inoue, Hideo Fujiwara:
TAM Design and Optimization for Transparency-Based SoC Test.
381-388
Electronic Edition (link) BibTeX
RF Test II
Design for Test
Testing Large Chips
Ensuring Secure Chips
Copyright © Sat May 16 23:47:01 2009
by Michael Ley (ley@uni-trier.de)
