ICCAD 2001:
San Jose,
California,
USA
International Conference on Computer-Aided Design,
November 4-8,
2001,
San Jose,
CA,
USA. ACM,
2001
Dynamic Verification
System-Level Exploration and Design
Interconnect Planning
Analog Macromodeling
Embedded Tutorial:
Platform-Based Designs
Embedded Tutorial:
VLSI Microsystems:
The Power of Many
Sequential Synthesis
Compiler Techniques in System Level Design
Routing Architecture and Techniques for FPGAs
Interconnect Performance and Reliability Optimization
Panel
Circuit Structure in Fromal Verification
System Level Power and Performance Modeling
- Giovanni Beltrame, Carlo Brandolese, William Fornaciari, Fabio Salice, Donatella Sciuto, Vito Trianni:
An Assembly-Level Execution-Time Model for Pipelined Architectures.
195-200
Electronic Edition (link) BibTeX
- Mahmut T. Kandemir, Ugur Sezer, Victor Delaluz:
Improving Memory Energy Using Access Pattern Classification.
201-206
Electronic Edition (link) BibTeX
- Radu Marculescu, Amit Nandi, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli:
System-Level Power/Performance Analysis of Portable Multimedia Systems Communicating over Wireless Channels.
207-
Electronic Edition (link) BibTeX
Topics in Physical Synthesis
Model Order Reduction
Embedded Tutorial:
Embedded Software and Systems
Embedded Tutorial
BDDs and SAT
- Lintao Zhang, Conor F. Madigan, Matthew W. Moskewicz, Sharad Malik:
Efficient Conflict Driven Learning in Boolean Satisfiability Solver.
279-285
Electronic Edition (link) BibTeX
- Aarti Gupta, Zijiang Yang, Pranav Ashar, Lintao Zhang, Sharad Malik:
Partition-Based Decision Heuristics for Image Computation Using SAT and BDDs.
286-292
Electronic Edition (link) BibTeX
- Pankaj Chauhan, Edmund M. Clarke, Somesh Jha, James H. Kukula, Thomas R. Shiple, Helmut Veith, Dong Wang:
Non-linear Quantification Scheduling in Image Computation.
293-
Electronic Edition (link) BibTeX
Convergence of Abstractions in High-Level Synthesis
Signal Integrity and Clock Design
Analog Synthesis
- Helmut E. Graeb, Stephan Zizala, Josef Eckmueller, Kurt Antreich:
The Sizing Rules Method for Analog Integrated Circuit Design.
343-349
Electronic Edition (link) BibTeX
- Michael Krasnicki, Rodney Phelps, James R. Hellums, Mark McClung, Rob A. Rutenbar, L. Richard Carley:
ASF: A Practical Simulation-Based Methodology for the Synthesis of Custom Analog Circuits.
350-357
Electronic Edition (link) BibTeX
- Peter J. Vancorenland, Geert Van der Plas, Michiel Steyaert, Georges G. E. Gielen, Willy M. C. Sansen:
A Layout-Aware Synthesis Methodology for RF Circuits.
358-
Electronic Edition (link) BibTeX
Manufacturing Test:
Stuck-at to Crosstalk
Architecture Oriented Scheduling
New Techniques in Routing
Issues in Substrate Coupling
Combinational Optimization
Real Time Scheduling and Performance Analysis
Power Analysis
Timing and Noise Analysis
System Level Test and Reliability
Power Issues in High Level Synthesis
Advances in Placement
Interconnect Analysis and Extraction
Don't Care Optimization and Boolean Matching
Power Saving Techniques for Embedded Processors
Embedded Tutorial:
IC Power Distribution Challenges
Panel
Copyright © Sat May 16 23:16:28 2009
by Michael Ley (ley@uni-trier.de)
