Volume 19,
Number 1,
January 2000
- C.-J. Richard Shi, Sheldon X.-D. Tan:
Canonical symbolic analysis of large analog circuits withdeterminant decision diagrams.
1-18
Electronic Edition (link) BibTeX
- Chantana Chantrapornchai, Edwin Hsing-Mean Sha, Xiaobo Sharon Hu:
Efficient design exploration based on module utility selection.
19-29
Electronic Edition (link) BibTeX
- Miodrag Potkonjak, Jan M. Rabaey:
Maximally and arbitrarily fast implementation of linear andfeedback linear computations.
30-43
Electronic Edition (link) BibTeX
- Youpyo Hong, Peter A. Beerel, Jerry R. Burch, Kenneth L. McMillan:
Sibling-substitution-based BDD minimization using don't cares.
44-55
Electronic Edition (link) BibTeX
- Steven J. E. Wilton:
Heterogeneous technology mapping for area reduction in FPGAs withembedded memory arrays.
56-68
Electronic Edition (link) BibTeX
- Mahbub Hasan, Huan-Hsiang Patrick Shen, David R. Allee, Michael J. Pennell:
A behavioral model of a 1.8-V flash A/D converter based on deviceparameters.
69-82
Electronic Edition (link) BibTeX
- Yehea I. Ismail, Eby G. Friedman, José Luis Neves:
Equivalent Elmore delay for RLC trees.
83-97
Electronic Edition (link) BibTeX
- Tuyen V. Nguyen, Anirudh Devgan, Ognen J. Nastov, David W. Winston:
Transient sensitivity computation in controlled explicit piecewiselinear simulation.
98-110
Electronic Edition (link) BibTeX
- Indradeep Ghosh, Niraj K. Jha, Sudipta Bhawmik:
A BIST scheme for RTL circuits based on symbolic testabilityanalysis.
111-128
Electronic Edition (link) BibTeX
- Wanli Jiang, Bapiraju Vinnakota:
IC test using the energy consumption ratio.
129-141
Electronic Edition (link) BibTeX
- Zheng Rong Yang, Mark Zwolinski, Chris D. Chalk, Alan Christopher Williams:
Applying a robust heteroscedastic probabilistic neural network toanalog fault detection and classification.
142-151
Electronic Edition (link) BibTeX
- Shih-Chieh Chang, Wen-Ben Jone, Shi-Sen Chang:
TAIR: testability analysis by implication reasoning.
152-160
Electronic Edition (link) BibTeX
- H. M. Chen, G. S. Samudra, D. S. H. Chan, Yaacob Ibrahim:
Global optimization for digital MOS circuits performance.
161-164
Electronic Edition (link) BibTeX
- Spiridon Nikolaidis, E. Karaolis, Efstathios D. Kyriakis-Bitzaros:
Estimation of signal transition activity in FIR filters implementedby a MAC architecture.
164-169
Electronic Edition (link) BibTeX
Volume 19,
Number 2,
February 2000
- Martin D. F. Wong, Dwight D. Hill:
Editorial.
173-174
Electronic Edition (link) BibTeX
- Piotr Berman, Andrew B. Kahng, Devendra Vidhani, Huijuan Wang, Alexander Zelikovsky:
Optimal phase conflict removal for layout of dark field alternatingphase shifting masks.
175-187
Electronic Edition (link) BibTeX
- Chieh Changfan, Yu-Chin Hsu, Fur-Shing Tsai:
Timing optimization on routed designs with incremental placementand routing characterization.
188-196
Electronic Edition (link) BibTeX
- Danqing Chen, Erhong Li, Elyse Rosenbaum, Sung-Mo Kang:
Interconnect thermal modeling for accurate simulation of circuittiming and reliability.
197-205
Electronic Edition (link) BibTeX
- Wei Chen, Cheng-Ta Hsieh, Massoud Pedram:
Simultaneous gate sizing and placement.
206-214
Electronic Edition (link) BibTeX
- Jason Cong, Jie Fang, Kei-Yong Khoo:
Via design rule consideration in multilayer maze routing algorithms.
215-223
Electronic Edition (link) BibTeX
- Kunihiro Fujiyoshi, Hiroshi Murata:
Arbitrary convex and concave rectilinear block packing usingsequence-pair.
224-233
Electronic Edition (link) BibTeX
- Sung-Woo Hur, Ashok Jagannathan, John Lillis:
Timing-driven maze routing.
234-241
Electronic Edition (link) BibTeX
- Dennis Sylvester, Kurt Keutzer:
A global wiring paradigm for deep submicron design.
242-252
Electronic Edition (link) BibTeX
- Ching-Han Tsai, Sung-Mo Kang:
Cell-level placement for improving substrate thermal distribution.
253-266
Electronic Edition (link) BibTeX
- Charles J. Alpert, Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov:
Hypergraph partitioning with fixed vertices [VLSI CAD].
267-272
Electronic Edition (link) BibTeX
- Evangeline F. Y. Young, Martin D. F. Wong, Hannah Honghua Yang:
Slicing floorplans with range constraint.
272-278
Electronic Edition (link) BibTeX
Volume 19,
Number 3,
March 2000
- Evguenii I. Goldberg, Luca P. Carloni, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Negative thinking in branch-and-bound: the case of unate covering.
281-294
Electronic Edition (link) BibTeX
- Hen-Ming Lin, Jing-Yang Jou:
On computing the minimum feedback vertex set of a directed graph bycontraction operations.
295-307
Electronic Edition (link) BibTeX
- Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha:
Incorporating speculative execution into scheduling ofcontrol-flow-intensive designs.
308-324
Electronic Edition (link) BibTeX
- Martin Bächtold, Mirko Spasojevic, Christian Lage, Per B. Ljung:
A system for full-chip and critical net parasitic extraction for ULSI interconnects using a fast 3-D field solver.
325-338
Electronic Edition (link) BibTeX
- Pasquale Cocchini, Massoud Pedram:
Fanout optimization using bipolar LT-trees.
339-349
Electronic Edition (link) BibTeX
- Guenter Stenz, Bernhard M. Riess, Bernhard Rohfleisch, Frank M. Johannes:
Performance optimization by interacting netlist transformations andplacement.
350-358
Electronic Edition (link) BibTeX
- Gerard A. Allan:
Yield prediction by sampling IC layout.
359-371
Electronic Edition (link) BibTeX
- Irith Pomeranz, Sudhakar M. Reddy:
On n-detection test sets and variable n-detection test sets fortransition faults.
372-383
Electronic Edition (link) BibTeX
- Rolf Drechsler, Nicole Drechsler, Wolfgang Günther:
Fast exact minimization of BDD's.
384-389
Electronic Edition (link) BibTeX
- Kyung Suk Oh:
Accurate transient simulation of transmission lines with the skineffect.
389-396
Electronic Edition (link) BibTeX
Volume 19,
Number 4,
April 2000
- Sheldon X.-D. Tan, C.-J. Richard Shi:
Hierarchical symbolic analysis of analog integrated circuits viadeterminant decision diagrams.
401-412
Electronic Edition (link) BibTeX
- Ian O'Connor, Andreas Kaiser:
Automated synthesis of current-memory cells.
413-424
Electronic Edition (link) BibTeX
- Kenneth L. Shepard, Zhong Tian:
Return-limited inductances: a practical approach to on-chipinductance extraction.
425-436
Electronic Edition (link) BibTeX
- Chauchin Su, Yue-Tsang Chen:
Intrinsic response extraction for the removal of the parasiticeffects in analog test buses.
437-445
Electronic Edition (link) BibTeX
- Jiang Hu, Sachin S. Sapatnekar:
Algorithms for non-Hanan-based optimization for VLSI interconnectunder a higher-order AWE model.
446-458
Electronic Edition (link) BibTeX
- Luca Benini, Giovanni De Micheli, Enrico Macii, Massimo Poncino, Riccardo Scarsi:
A multilevel engine for fast power simulation of realistic inputstreams.
459-472
Electronic Edition (link) BibTeX
- Jennifer Y. Dong, Ajoy Opal:
Time-domain thermal noise simulation of switched capacitor circuitsand delta-sigma modulators.
473-481
Electronic Edition (link) BibTeX
- Hong-Yean Hsieh, Wentai Liu, Ralph K. Cavin III:
Integrated parametric timing optimization of digital systems.
482-489
Electronic Edition (link) BibTeX
- Jue Wu, Elizabeth M. Rudnick:
Bridge fault diagnosis using stuck-at fault simulation.
489-495
Electronic Edition (link) BibTeX
Volume 19,
Number 5,
May 2000
- Wendy Belluomini, Chris J. Myers:
Timed state space exploration using POSETs.
501-520
Electronic Edition (link) BibTeX
- Christoph Meinel, Fabio Somenzi, Thorsten Theobald:
Linear sifting of decision diagrams and its application insynthesis.
521-533
Electronic Edition (link) BibTeX
- Shantanu Dutt, Wenyong Deng:
Probability-based approaches to VLSI circuit partitioning.
534-549
Electronic Edition (link) BibTeX
- Sachin S. Sapatnekar:
A timing model incorporating the effect of crosstalk on delay andits application to optimal channel routing.
550-559
Electronic Edition (link) BibTeX
- Andreas Hössinger, Erasmus Langer, Siegfried Selberherr:
Parallelization of a Monte Carlo ion implantation simulator.
560-567
Electronic Edition (link) BibTeX
- Sreejit Chakravarty, Sujit T. Zachariah:
STBM: a fast algorithm to simulate IDDQ tests forleakage faults.
568-576
Electronic Edition (link) BibTeX
- Kun-Jin Lin, Cheng-Wen Wu:
Testing content-addressable memories using functional fault modelsand march-like algorithms.
577-588
Electronic Edition (link) BibTeX
- Irith Pomeranz, Sudhakar M. Reddy:
A diagnostic test generation procedure based on test elimination byvector omission for synchronous sequential circuits.
589-600
Electronic Edition (link) BibTeX
- Pallab Dasgupta, Jatindra Kumar Deka, Partha Pratim Chakrabarti:
Model checking on timed-event structures.
601-611
Electronic Edition (link) BibTeX
- Jun Dong Cho:
Wiring space and length estimation in two-dimensional arrays.
612-615
Electronic Edition (link) BibTeX
- Taewhan Kim, Junhyung Um:
A practical approach to the synthesis of arithmetic circuits usingcarry-save-adders.
615-624
Electronic Edition (link) BibTeX
- Xiaoyu Song, Qian-Yu Tang, Dian Zhou, Yuke Wang:
Wire space estimation and routability analysis.
624-628
Electronic Edition (link) BibTeX
Volume 19,
Number 6,
June 2000
- Edoardo Charbon:
Guest Editorial.
633-634
Electronic Edition (link) BibTeX
- Resve A. Saleh, Syed Zakir Hussain, Steffen Rochel, David Overhauser:
Clock skew verification in the presence of IR-drop in the powerdistribution network.
635-644
Electronic Edition (link) BibTeX
- J. Briaire, K. S. Krisch:
Principles of substrate crosstalk generation in CMOS circuits.
645-653
Electronic Edition (link) BibTeX
- Akio Koyama, Makio Uchida, Tatsuhiro Aida, Jun'ya Kudo, Masatoshi Tsuge:
Switching well noise modeling and minimization strategy for digitalcircuits with a controllable threshold voltage scheme.
654-670
Electronic Edition (link) BibTeX
- Makoto Nagata, Jin Nagai, Takashi Morie, Atsushi Iwata:
Measurements and analyses of substrate noise waveform inmixed-signal IC environment.
671-678
Electronic Edition (link) BibTeX
- Chandramouli Visweswariah, Ruud A. Haring, Andrew R. Conn:
Noise considerations in circuit optimization.
679-690
Electronic Edition (link) BibTeX
- Prashant Saxena, C. L. Liu:
A postprocessing algorithm for crosstalk-driven wire perturbation.
691-702
Electronic Edition (link) BibTeX
- Rodney Phelps, Michael Krasnicki, Rob A. Rutenbar, L. Richard Carley, James R. Hellums:
Anaconda: simulation-based synthesis of analog circuits viastochastic pattern search.
703-717
Electronic Edition (link) BibTeX
Volume 19,
Number 7,
July 2000
- Florin Balasa, Koen Lampaert:
Symmetry within the sequence-pair representation in the context ofplacement for analog design.
721-731
Electronic Edition (link) BibTeX
- Jui-Ming Chang, Massoud Pedram:
Codex-dp: co-design of communicating systems using dynamicprogramming.
732-744
Electronic Edition (link) BibTeX
- Zhao-Xuan Shen, Ching Chuen Jong:
Functional area lower bound and upper bound on multicomponentselection for interval scheduling.
745-759
Electronic Edition (link) BibTeX
- Fabrizio Ferrandi, Franco Fummi, Enrico Macii, Massimo Poncino, Donatella Sciuto:
Symbolic optimization of interacting controllers based onredundancy identification and removal.
760-772
Electronic Edition (link) BibTeX
- Dingming Xie, Leonard Forbes:
Phase noise on a 2-GHz CMOS LC oscillator.
773-778
Electronic Edition (link) BibTeX
- Kishore Kasamsetty, Mahesh Ketkar, Sachin S. Sapatnekar:
A new class of convex functions for delay modeling and itsapplication to the transistor sizing problem [CMOS gates].
779-788
Electronic Edition (link) BibTeX
- Bapiraju Vinnakota, Ramesh Harjani:
DFT for digital detection of analog parametric faults in SC filters.
789-798
Electronic Edition (link) BibTeX
- Pavan K. Gunupudi, Michel S. Nakhla, Ramachandra Achar:
Simulation of high-speed distributed interconnects usingKrylov-space techniques.
799-808
Electronic Edition (link) BibTeX
- Subodh Gupta, Farid N. Najm:
Analytical models for RTL power estimation of combinational andsequential circuits.
808-814
Electronic Edition (link) BibTeX
- C. A. J. van Eijk:
Sequential equivalence checking based on structural similarities.
814-819
Electronic Edition (link) BibTeX
- Hai Zhou, Martin D. F. Wong, I-Min Liu, Adnan Aziz:
Simultaneous routing and buffer insertion with restrictions onbuffer locations.
819-824
Electronic Edition (link) BibTeX
Volume 19,
Number 8,
August 2000
- Tamal Mukherjee, L. Richard Carley, Rob A. Rutenbar:
Efficient handling of operating range and manufacturing linevariations in analog cell synthesis.
825-839
Electronic Edition (link) BibTeX
- Shigeru Yamashita, Hiroshi Sawada, Akira Nagoya:
SPFD: A new method to express functional flexibility.
840-849
Electronic Edition (link) BibTeX
- Pak K. Chan, Martine D. F. Schlag, Carl Ebeling, Larry McMurchie:
Distributed-memory parallel routing for field-programmable gatearrays.
850-862
Electronic Edition (link) BibTeX
- Indradeep Ghosh, Sujit Dey, Niraj K. Jha:
A fast and low-cost testing technique for core-based system-chips.
863-877
Electronic Edition (link) BibTeX
- Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer:
Cellular automata-based test pattern generators with phase shifters.
878-893
Electronic Edition (link) BibTeX
- Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha:
TAO-BIST: A framework for testability analysis and optimization forbuilt-in self-test of RTL circuits.
894-906
Electronic Edition (link) BibTeX
- Paul Tafertshofer, Andreas Ganz, Kurt Antreich:
IGRAINE-an Implication GRaph-bAsed engINE for fast implication, justification, and propagation.
907-927
Electronic Edition (link) BibTeX
- Huan-Chih Tsai, Kwang-Ting Cheng, Sudipta Bhawmik:
On improving test quality of scan-based BIST.
928-938
Electronic Edition (link) BibTeX
- Karsten Strehl, Lothar Thiele:
Interval diagrams for efficient symbolic verification of processnetworks.
939-956
Electronic Edition (link) BibTeX
- Ilker Hamzaoglu, Janak H. Patel:
Test set compaction algorithms for combinational circuits.
957-963
Electronic Edition (link) BibTeX
- Ming-Bo Lin:
On the design of fast large fan-in CMOS multiplexers.
963-967
Electronic Edition (link) BibTeX
Volume 19,
Number 9,
September 2000
- Luca Benini, Alberto Macii, Massimo Poncino, Riccardo Scarsi:
Architectures and synthesis algorithms for power-efficient businterfaces.
969-980
Electronic Edition (link) BibTeX
- Norman Scheinberg, Aleksey Pinkhasov:
A computer simulation model for simulating distortion in FETresistors.
981-989
Electronic Edition (link) BibTeX
- Zheng-Yu Yuan, Zheng-Fan Li, Min-Liu Zou:
Computer-aided analysis of on-chip interconnects near semiconductorsubstrate for high-speed VLSI.
990-998
Electronic Edition (link) BibTeX
- Iris Hui-Ru Jiang, Yao-Wen Chang, Jing-Yang Jou:
Crosstalk-driven interconnect optimization by simultaneous gate andwire sizing.
999-1010
Electronic Edition (link) BibTeX
- Dirk Stroobandt, Peter Verplaetse, Jan M. Van Campenhout:
Generating synthetic benchmark circuits for evaluating CAD tools.
1011-1022
Electronic Edition (link) BibTeX
- Koichi Nose, Takayasu Sakurai:
Analysis and future trend of short-circuit power.
1023-1030
Electronic Edition (link) BibTeX
- Bin-Hong Lin, Shao-Hui Shieh, Cheng-Wen Wu:
A fast signature computation algorithm for LFSR and MISR.
1031-1040
Electronic Edition (link) BibTeX
- Debjyoti Paul, Mitrajit Chatterjee, Dhiraj K. Pradhan:
VERILAT: verification using logic augmentation and transformations.
1041-1051
Electronic Edition (link) BibTeX
- Kun-Han Tsai, Janusz Rajski, Malgorzata Marek-Sadowska:
Star test: the theory and its applications.
1052-1064
Electronic Edition (link) BibTeX
- Gianpiero Cabodi, Paolo Camurati, Stefano Quer:
Improving symbolic reachability analysis by means of activityprofiles.
1065-1075
Electronic Edition (link) BibTeX
- Susanta Chakrabarti, Sandip Das, Debesh Kumar Das, Bhargab B. Bhattacharya:
Synthesis of symmetric functions for path-delay fault testability.
1076-1081
Electronic Edition (link) BibTeX
- Craig M. Files, Marek A. Perkowski:
New multivalued functional decomposition algorithms based on MDDs.
1081-1086
Electronic Edition (link) BibTeX
- Irith Pomeranz, Sudhakar M. Reddy:
On synchronizable circuits and their synchronizing sequences.
1086-1092
Electronic Edition (link) BibTeX
Volume 19,
Number 10,
October 2000
- Henrik Hulgaard, Tod Amon:
Symbolic timing analysis of asynchronous systems.
1093-1104
Electronic Edition (link) BibTeX
- Vijay Raghunathan, Srivaths Ravi, Ganesh Lakshminarayana:
Integrating variable-latency components into high-level synthesis.
1105-1117
Electronic Edition (link) BibTeX
- Christopher S. Helvig, Gabriel Robins, Alexander Zelikovsky:
New approximation algorithms for routing with multiport terminals.
1118-1128
Electronic Edition (link) BibTeX
- Ion I. Mandoiu, Vijay V. Vazirani, Joseph L. Ganley:
A new heuristic for rectilinear Steiner trees.
1129-1139
Electronic Edition (link) BibTeX
- Maogang Wang, Xiaojian Yang, Majid Sarrafzadeh:
Congestion minimization during placement.
1140-1148
Electronic Edition (link) BibTeX
- Adnan Aziz, Felice Balarin, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Sequential synthesis using S1S.
1149-1162
Electronic Edition (link) BibTeX
- Krishnendu Chakrabarty:
Test scheduling for core-based systems using mixed-integer linearprogramming.
1163-1174
Electronic Edition (link) BibTeX
- Janusz Rajski, Nagesh Tamarapalli, Jerzy Tyszer:
Automated synthesis of phase shifters for built-in self-testapplications.
1175-1188
Electronic Edition (link) BibTeX
- Pramodchandran N. Variyam, Abhijit Chatterjee:
Specification-driven test generation for analog circuits.
1189-1201
Electronic Edition (link) BibTeX
- Seungjoon Park, Satyaki Das, David L. Dill:
Automatic checking of aggregation abstractions through stateenumeration.
1202-1210
Electronic Edition (link) BibTeX
- Yi-Kan Cheng, Sung-Mo Kang:
A temperature-aware simulation environment for reliable ULSI chipdesign.
1211-1220
Electronic Edition (link) BibTeX
- Haksu Kim, Dian Zhou:
Efficient implementation of a planar clock routing with thetreatment of obstacles.
1220-1225
Electronic Edition (link) BibTeX
- Aiguo Xie, Peter A. Beerel:
Implicit enumeration of strongly connected components and anapplication to formal verification.
1225-1230
Electronic Edition (link) BibTeX
Volume 19,
Number 11,
November 2000
- Robert Kosik, Peter Fleischmann, Bernhard Haindl, Paola Pietra, Siegfried Selberherr:
On the interplay between meshing and discretization inthree-dimensional diffusion simulation.
1233-1240
Electronic Edition (link) BibTeX
- Andrea Pacelli, Marco Mastrapasqua, Serge Luryi:
Generation of equivalent circuits from physics-based devicesimulation.
1241-1250
Electronic Edition (link) BibTeX
- Shantanu Tarafdar, Miriam Leeser:
A data-centric approach to high-level synthesis.
1251-1267
Electronic Edition (link) BibTeX
- Jason Cong, Songjie Xu:
Performance-driven technology mapping for heterogeneous FPGAs.
1268-1281
Electronic Edition (link) BibTeX
- Nasser Masoumi, Mohamed I. Elmasry, Safieddin Safavi-Naeini:
Fast and efficient parametric modeling of contact-to-substratecoupling.
1282-1292
Electronic Edition (link) BibTeX
- Dingming Xie, Mengzhang Cheng, Leonard Forbes:
SPICE models for flicker noise in n-MOSFETs from subthreshold tostrong inversion.
1293-1303
Electronic Edition (link) BibTeX
- Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov:
Optimal partitioners and end-case placers for standard-cell layout.
1304-1313
Electronic Edition (link) BibTeX
- Joachim Pistorius, Edmée Legai, Michel Minoux:
PartGen: a generator of very large circuits to benchmark thepartitioning of FPGAs.
1314-1321
Electronic Edition (link) BibTeX
- Min Zhao, Sachin S. Sapatnekar:
Timing-driven partitioning and timing optimization of mixedstatic-domino implementations.
1322-1336
Electronic Edition (link) BibTeX
- Sachio Hayashi, Masaaki Yamada:
EMI-noise analysis under ASIC design environment.
1337-1346
Electronic Edition (link) BibTeX
- Mukund Sivaraman, Andrzej J. Strojwas:
Primitive path delay faults: identification and their use in timinganalysis.
1347-1362
Electronic Edition (link) BibTeX
- Zhanping Chen, Kaushik Roy, Edwin K. P. Chong:
Estimation of power dissipation using a novel power macromodelingtechnique.
1363-1369
Electronic Edition (link) BibTeX
- Tong Liu, Wei-Kang Huang, Fred J. Meyer, Fabrizio Lombardi:
Testing and testable designs for one-time programmable FPGAs.
1370-1375
Electronic Edition (link) BibTeX
- Nicola Nicolici, Bashir M. Al-Hashimi, Andrew D. Brown, Alan Christopher Williams:
BIST hardware synthesis for RTL data paths based on testcompatibility classes.
1375-1385
Electronic Edition (link) BibTeX
- Jon T. Butler, Gerhard W. Dueck, Vlad P. Shmerko, Svetlana N. Yanushkevich:
Comments on "Sympathy: fast exact minimization of fixedpolarity Reed-Muller expansion for symmetric functions".
1386-1388
Electronic Edition (link) BibTeX
- Xiaodong Zhang, Wenlei Shan, Kaushik Roy:
Low-power weighted random pattern testing.
1389-1398
Electronic Edition (link) BibTeX
Volume 19,
Number 12,
December 2000
- Raul Camposano, Massoud Pedram:
Electronic design automation at the turn of the century: accomplishments and vision of the future.
1401-1403
Electronic Edition (link) BibTeX
- Jochen A. G. Jess:
Designing electronic engines with electronic engines: 40 years ofbootstrapping of a technology upon itself.
1404-1427
Electronic Edition (link) BibTeX
- Don MacMillen, Raul Camposano, Dwight D. Hill, Thomas W. Williams:
An industrial view of electronic design automation.
1428-1448
Electronic Edition (link) BibTeX
- Melvin A. Breuer, Majid Sarrafzadeh, Fabio Somenzi:
Fundamental CAD algorithms.
1449-1475
Electronic Edition (link) BibTeX
- John A. Darringer, Evan E. Davidson, David J. Hathaway, Bernd Koenemann, Mark A. Lavin, Joseph K. Morrell, Khalid Rahmat, Wolfgang Roesner, Erich C. Schanzenbach, Gustavo Tellez, Louise Trevillyan:
EDA in IBM: past, present, and future.
1476-1497
Electronic Edition (link) BibTeX
- T. Karn, Shishpal Rawat, Desmond Kirkpatrick, Rabindra K. Roy, Greg Spirakis, Naveed A. Sherwani, Craig Peterson:
EDA challenges facing future microprocessor design.
1498-1506
Electronic Edition (link) BibTeX
- K. Wakabayashi, T. Okamoto:
C-based SoC design flow and EDA tools: an ASIC and system vendorperspective.
1507-1522
Electronic Edition (link) BibTeX
- Kurt Keutzer, A. Richard Newton, Jan M. Rabaey, Alberto L. Sangiovanni-Vincentelli:
System-level design: orthogonalization of concerns andplatform-based design.
1523-1543
Electronic Edition (link) BibTeX
- Robert W. Dutton, Andrzej J. Strojwas:
Perspectives on technology and technology-driven CAD.
1544-1560
Electronic Edition (link) BibTeX
- Kenneth S. Kundert, Henry Chang, Dan Jefferies, Gilles Lamant, Enrico Malavasi, Fred Sendig:
Design of mixed-signal systems-on-a-chip.
1561-1571
Electronic Edition (link) BibTeX
- Tamal Mukherjee, Gary K. Fedder, Deepak Ramaswamy, Jacob K. White:
Emerging simulation approaches for micromachined devices.
1572-1589
Electronic Edition (link) BibTeX
Copyright © Sun May 17 00:23:12 2009
by Michael Ley (ley@uni-trier.de)