VTS 2002: Monterey, CA, USA

20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April - 2 May 2002, Monterey, CA, USA. IEEE Computer Society 2002, ISBN 0-7695-1570-3 BibTeX

Microprocessor Test: Moderators: M. d'Abreau, Ample Communications

Nandu Tendolkar, Rajesh Raina, Rick Woltenberg, Xijiang Lin, Bruce Swanson, Greg Aldrich:
Novel Techniques for Achieving High At-Speed Transition Fault Test Coverage for Motorola's Microprocessors Based on PowerPC(tm) Instruction Set Architecture. 3-8
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Amit R. Pandey, Janak H. Patel:
Reconfiguration Technique for Reducing Test Time and Test Data Volume in Illinois Scan Architecture Based Designs . 9-15
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Dilip K. Bhavsar, Richard A. Davies:
Scan Islands - A Scan Partitioning Architecture and its Implementation on the Alpha 21364 Processor. 16-24
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Applications of Very Low Voltage and Slow Speed Testing

Eric MacDonald, Nur A. Touba:
Very Low Voltage Testing of SOI Integrated Circuits. 25-30
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Wanli Jiang, Erik Peterson:
Performance Comparison of VLV, ULV, and ECR Tests. 31-36
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Chao-Wen Tseng, James Li, Edward J. McCluskey:
Experimental Results for Slow-Speed Testing. 37-42
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Innovations in Test Automation

J. Borel, Anand Raghunathan, Jim Sproch, Michael Howells, Janusz Rajski:
Innovations in Test Automation. 43-46
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Advancements in Scan-Based Testing

Michael Gössel, Egor S. Sogomonyan, Adit D. Singh:
Scan-Path with Directly Duplicated and Inverted Duplicated Registers. 47-52
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Aiman El-Maleh, Ali Al-Suwaiyan:
An Efficient Test Relaxation Technique for Combinational & Full-Scan Sequential Circuits. 53-59
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Karim Arabi:
Logic BIST and Scan Test Techniques for Multiple Identical Blocks. 60-68
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Burn-in Reduction or Alternatives

Robert Madge, Manu Rehani, Kevin Cota, W. Robert Daasch:
Statistical Post-Processing at Wafersort - An Alternative to Burn-in and a Manufacturable Solution to Test Limit Setting for Sub-micron Technologies. 69-74
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Thomas S. Barnett, Adit D. Singh, Matt Grady, Kathleen G. Purdy:
Yield-Reliability Modeling: Experimental Verification and Application to Burn-In Reduction. 75-80
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Sagar S. Sabade, D. M. H. Walker:
Evaluation of Effectiveness of Median of Absolute Deviations Outlier Rejection-based IDDQ Testing for Burn-in Reduction. 81-86
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DFT Testers 1

Lee Song, Rudy Garcia, Andrew Levy, Donald L. Wheater:
A Successful DFT Tester: What Will It Look Like? Is Revolution in Test Approaches Required? 87-90
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Test Set Compression Techniques

Anshuman Chandra, Krishnendu Chakrabarty, Rafael A. Medina:
How Effective are Compression Codes for Reducing Test Data Volume? 91-96
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Ajay Khoche, Erik H. Volkerink, Jochen Rivoir, Subhasish Mitra:
Test Vector Compression Using EDA-ATE Synergies. 97-102
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Sudhakar M. Reddy, Kohei Miyase, Seiji Kajihara, Irith Pomeranz:
On Test Data Volume Reduction for Multiple Scan Chain Designs. 103-110
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Analog BIST

Ganapathy Kasturirangan, Michael S. Hsiao:
Spectrum-Based BIST in Complex SOCs. 111-116
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Hung-kai Chen, Chih-hu Wang, Chau-chin Su:
A Self Calibrated ADC BIST Methodology. 117-122
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Chee-Kian Ong, Kwang-Ting (Tim) Cheng:
Self-Testing Second-Order Delta-Sigma Modulators Using Digital Stimulus. 123-128
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DFT Testers 2

Bill Bottoms, Lee Song, Paul Patton, Wilhelm Radermacher:
A Successful DFT Tester: What Will It Look Like? Is DFT Tester a Logical Next Step in ATE Evolution? 129-132
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Increased Efficiency Testing

Mehrdad Nourani, James Chin:
Testing High-Speed SoCs Using Low-Speed ATEs. 133-138
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Madhu K. Iyer, Kwang-Ting Cheng:
Software-Based Weighted Random Testing for IP Cores in Bus-Based Programmable SoCs. 139-144
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René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
On Using Efficient Test Sequences for BIST. 145-152
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Controlling and Reducing Test Power

Ranganathan Sankaralingam, Nur A. Touba:
Controlling Peak Power During Scan Testing. 153-159
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Seiji Kajihara, Koji Ishida, Kohei Miyase:
Test Vector Modification for Power Reduction during Scan Testing. 160-165
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Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailoglu:
Test Power Reduction through Minimization of Scan Chain Transitions. 166-172
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IP Session 4

Robert C. Aitken, Mustapha Slamani, H. Ding, William R. Eisenstadt, Sanghoon Choi, John McLaughlin:
Wireless Test. 173-174
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Panel

Adam Osseiran, William De Wilkins, Barry Baril, Sassan Tabatabaei, Fidel Muradali, Ken Posse, Lee Song:
Analog and Mixed Signal BIST: Too Much, Too Little, Too Late? 175-176
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Julie Segal, Rene Segers, Rob Aitken, S. Eichenberge, A. Gattike, M. Millegen, R. Seger, S. Venkataraman:
Test as a Key Enabler for Faster Yield Ramp-Up. 177-180
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Diagnosis

Enamul Amyeen, Irith Pomeranz, W. Kent Fuchs:
Theorems for Efficient Identification of Indistinguishable Fault Pairs in Synchronous Sequential Circuits. 181-186
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Chien-Mo James Li, Edward J. McCluskey:
Diagnosis of Sequence-Dependent Chips. 187-192
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Shi-Yu Huang:
Speeding Up The Byzantine Fault Diagnosis Using Symbolic Simulation. 193-200
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Analog Circuit Testing

José Vicente Calvano, Vladimir Castro Alves, Antônio C. Mesquita, Marcelo Lubaszewski:
Filters Designed for Testability Wrapped on the Mixed-Signal Test Bus. 201-206
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Takahiro J. Yamaguchi, Masahiro Ishida, Mani Soma, Louis Malarsie, Hirobumi Musha:
Timing Jitter Measurement of 10 Gbps Bit Clock Signals Using Frequency Division. 207-212
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Sule Ozev, Alex Orailoglu:
Boosting the Accuracy of Analog Test Coverage Computation through Statistical Tolerance Analysis. 213-222
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High Level Test Techniques

Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos, Yervant Zorian:
Instruction-Based Self-Testing of Processor Cores. 223-228
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Luis Berrojo, Isabel González, Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero, Luis Entrena, Celia López:
An Industrial Environment for High-Level Fault-Tolerant Structures Insertion and Validation. 229-236
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Vivekananda M. Vedula, Jacob A. Abraham, Jayanta Bhadra:
Program Slicing for Hierarchical Test Generation. 237-246
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SoC Test Infrastructure

Subhasish Mitra, Edward J. McCluskey, Samy Makar:
Design for Testability and Testing of IEEE 1149.1 Tap Controller. 247-252
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Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen:
On Using Rectangle Packing for SOC Wrapper/TAM Co-Optimization. 253-258
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Sandeep Kumar Goel, Erik Jan Marinissen:
Cluster-Based Test Architecture Design for System-on-Chip. 259-264
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Multi-GigaHertz Testing Challenges and Solutions

Karim Arabi, Klaus-Dieter Hilliges, David C. Keezer, Sassan Tabatabaei:
Multi-GigaHertz Testing Challenges and Solutions. 265-268
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Test Tools and Algorithms

Kumar N. Dwarakanath, R. D. (Shawn) Blanton:
Exploiting Dominance and Equivalence using Fault Tuples. 269-274
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Narayanan Krishnamurthy, Jayanta Bhadra, Magdy S. Abadir, Jacob A. Abraham:
Is State Mapping Essential for Equivalence Checking Custom Memories in Scan-Based Designs? 275-280
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Kuo-Liang Cheng, Jen-Chieh Yeh, Chih-Wea Wang, Chih-Tsun Huang, Cheng-Wen Wu:
RAMSES-FT: A Fault Simulator for Flash Memory Testing and Diagnostics. 281-288
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Supply Current Testing

Yukio Okuda:
Eigen-Signatures for Regularity-based IDDQ Testing. 289-294
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Claude Thibeault:
Speeding-Up IDDQ Measurements. 295-301
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Swarup Bhunia, Kaushik Roy:
Dynamic Supply Current Testing of Analog Circuits Using Wavelet Transform. 302-310
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Panel

Edward J. McCluskey, Subhasish Mitra, Bob Madge, Peter C. Maxwell, Phil Nigh, Mike Rodgers:
Debating the Future of Burn-In. 311-314
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Hot Topic

B. Courtoi, M. Forshaw:
Beyond CMOS. 315-316
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Embedded Tutorial

G. Roberts:
Challenges of Mixed-Signal Board Design and Test. 317-320
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Test Pattern Generation

Satoshi Ohtake, Hideo Fujiwara, Shunjiro Miwa:
A Method of Test Generation for Path Delay Faults in Balanced Sequential Circuits. 321-327
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Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka:
A Test Generation Method Using a Compacted Test Table and a Test Generation Method Using a Compacted Test Plan Table for RTL Data Path Circuits. 328-335
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Amir Attarha, Mehrdad Nourani:
Test Pattern Generation for Signal Integrity Faults on Long Interconnects. 336-344
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Tester Hardware Modeling and Improvements

Rodger Schuttert, Frans de Jong, Ben Kup:
Improved Test Monitor Circuit in Power Pin DfT. 345-350
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Achintya Halder, Abhijit Chatterjee, Pramodchandran N. Variyam, John Ridley:
Measuring Stray Capacitance on Tester Hardware. 351-356
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Abhishek Singh, Jim Plusquellic, Anne E. Gattiker:
Power Supply Transient Signal Analysis Under Real Process and Test Hardware Models. 357-366
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Fault Modeling & Extraction

Sreejit Chakravarty, Kambiz Komeyli, Eric W. Savage, Michael J. Carruthers, Bret T. Stastny, Sujit T. Zachariah:
Layout Analysis to Extract Open Nets Caused by Systematic Failure Mechanisms. 367-372
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Sreejit Chakravarty, Ankur Jain:
Fault Models for Speed Failures Caused by Bridges and Opens. 373-378
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Rahul Kundu, R. D. (Shawn) Blanton:
Timed Test Generation Crosstalk Switch Failures in Domino CMOS Circuits. 379-388
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Memory Testing

Jin-Fu Li, Ruey-Shing Tzeng, Cheng-Wen Wu:
Testing and Diagnosing Embedded Content Addressable Memories. 389-394
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Said Hamdioui, Zaid Al-Ars, A. J. van de Goor:
Testing Static and Dynamic Faults in Random Access Memories. 395-400
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Zaid Al-Ars, A. J. van de Goor:
Approximating Infinite Dynamic Behavior for DRAM Cell Defects. 401-406
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IP Session 8

C.-H. Chia, Sujit Dey, Faraydon Karim, Haluk Konuk, Keesup Kim:
Validation and Test of Network Processors and ASICs. 407-410
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Test-Cost Reduction

Erik H. Volkerink, Ajay Khoche, Jochen Rivoir, Klaus D. Hilliges:
Test Economics for Multi-site Test with Modern Cost Reduction Techniques. 411-416
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Krishna Sekar, Sujit Dey:
LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects. 417-422
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Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici:
Useless Memory Allocation in System-on-a-Chip Test: Problems and Solutions. 423-432
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Oscillation - Based Test

Diego Vázquez, Gloria Huertas, Gildas Leger, Adoración Rueda, José L. Huertas:
Practical Solutions for the Application of the Oscillation-Based-Test: Start-Up and On-Chip Evaluation. 433-438
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Vincent Beroulle, Yves Bertrand, Laurent Latorre, Pascal Nouet:
Evaluation of the Oscillation-based Test Methodology for Micro-Electro-Mechanical Systems. 439-444
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Panel

Fidel Muradali, Mike Ricchetti, Bart Vermeulen, Bulent I. Dervisoglu, Bob Gottlieb, Bernd Koenemann, C. J. Clark:
Reducing Time to Volume and Time to Market: Is Silicon Debug and Diagnosis the Answer? 445-446
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Embedded Tutorial

Jaume Segura, Vivek De, Ali Keshavarzi:
Challenges in Nanometric Technology Scaling: Trends and Projections. 447-448
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Panel

Salvador Mir, H. Bederr, R. D. (Shawn) Blanton, Hans G. Kerkhoff, H. J. Klim:
SoCs with MEMS? Can We Include MEMS in the SoCs Design and Test Flow? 449-450
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