12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China.
IEEE Computer Society 2003, ISBN 0-7695-1951-2 BibTeX
@proceedings{DBLP:conf/ats/2003,
title = {12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian,
China},
booktitle = {Asian Test Symposium},
publisher = {IEEE Computer Society},
year = {2003},
isbn = {0-7695-1951-2},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Keynote Address
Design for Testabilit
- Hiroyuki Yotsuyanagi, Toshimasa Kuchii, Shigeki Nishikawa, Masaki Hashizume, Kozo Kinoshita:
Reducing Scan Shifts Using Folding Scan Trees.
6-11
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- Dong Xiang, Ming-Jing Chen, Jia-Guang Sun, Hideo Fujiwara:
Improving Test Quality of Scan-Based BIST by Scan Chain Partitioning.
12-17
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- Xiangdong Xuan, Abhijit Chatterjee, Adit D. Singh, Namsoo P. Kim, Mark T. Chisa:
IC Reliability Simulator ARET and Its Application in Design-for-Reliability.
18-23
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Memory Testing 1
- Zaid Al-Ars, A. J. van de Goor:
Analyzing the Impact of Process Variations on DRAM Testing Using Border Resistance Traces.
24-27
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- Yuki Yamagata, Kenichi Ichino, Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki, Masayuki Satoh, Hiroyuki Itabashi, Takashi Murai, Nobuyuki Otsuka:
Implementation of Memory Tester Consisting of SRAM-Based Reconfigurable Cells.
28-31
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- Fabrizio Bertuccelli, Franco Bigongiari, Andrea S. Brogna, Giorgio Di Natale, Paolo Prinetto, Roberto Saletti:
Exhaustive Test of Several Dependable Memory Architectures Designed by GRAAL Tool.
32-37
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Fault Diagnosis 1
Delay Testing
BIST
Software Testing 1
Mixed-Signal Testing
Test Compaction 1
RTL Verification
Enhanced Delay Testing and ATPG
- Michel Renovell, Jean Marc Gallière, Florence Azaïs, Yves Bertrand:
Delay Testing of MOS Transistor with Gate Oxide Short.
168-173
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- Arani Sinha, Sandeep K. Gupta, Melvin A. Breuer:
An Enhanced Test Generator for Capacitance Induced Crosstalk Delay Faults.
174-177
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- Huawei Li, Yue Zhang, Xiaowei Li:
Delay Test Pattern Generation Considering Crosstalk-Induced Effects.
178-183
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- Magdy S. Abadir, Jing Zeng, Carol Pyron, Juhong Zhu:
Automated Test Model Generation from Switch Level Custom Circuits.
184-189
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Test Power
Software Testing 2
Fault Diagnosis
Memory Testing 2
SOC Test
DFT Synthesis
Test Scheduling
Measurement
Test Economics
Memory Testing 3
Current Test
- Masaki Hashizume, Teppei Takeda, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Yukiya Miura, Kozo Kinoshita:
A BIST Circuit for IDDQ Tests.
390-395
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- Yinghua Min, Jishun Kuang, Xiaoyan Niu:
At-Speed Current Testing.
396-399
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- Jishun Kuang, Yu Wang, Xiaofen Wei, Changnian Zhang:
IDDT ATPG Based on Ambiguous Delay Assignments.
400-405
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- Hiroyuki Michinishi, Tokumi Yokohira, Takuji Okamoto, Toshifumi Kobayashi, Tsutomu Hondo:
Improvement of Detectability for CMOS Floating Gate Defects in Supply Current Test.
406-411
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SOC DFT
Test Compaction 2
Functional Testing/Reliability
- Gaocai Wang, Jianer Chen, Guojun Wang, Songqiao Chen:
Probability Model for Faults in Large-Scale Multicomputer Systems.
452-457
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- Ling Liu, Wennan Feng, Song Jia, Anping Jiang, Lijiu Ji:
Design Retargetable Platform System for Microprocessor Functional Test.
458-461
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- Piotr Gawkowski, Janusz Sosnowski:
Assessing Software Implemented Fault Detection and Fault Tolerance Mechanisms.
462-467
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- Fabian Vargas, Rubem Dutra Ribeiro Fagundes, Daniel Barros Jr., Diogo B. Brum:
Briefing a New Approach to Improve the EMI Immunity of DSP Systems.
468-473
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Formal Verification
Software Testing 3
Poster Session
- Li Shen:
RTL Concurrent Fault Simulation.
502
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- Ming Zhu, Jinian Bian, Weimin Wu, Hongxi Xue:
Property Classification for Functional Verification Based.
503
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- Jian-Hui Jiang:
Error Detection and Correction in VLSI Systems by Online Testing and Retrying.
504
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- Saeed Safari, Hadi Esmaeilzadeh, Amir-Hossein Jahangir:
Testability Improvement During High-Level Synthesis.
505
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- Yong-sheng Wang, Liyi Xiao, Mingyan Yu, Jinxiang Wang, Yizheng Ye:
A Test Architecture for System-on-a-Chip.
506
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- He Hu, Yihe Sun:
Test-Point Selection Algorithm Using Small Signal Model for Scan-Based BIST.
507
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- Junichi Hirase:
Test Pattern Length Required to Reach the Desired Fault Coverage.
508
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- Zhongwei Xu, Bangxing Chen:
Damage Size and Software Safety Demonstration Stress Testing.
509
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- Meng Li, Zhu Xu:
Study on the Cost/Benefit/Optimization of Software Safety Test.
510
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Copyright © Sat May 16 22:59:04 2009
by Michael Ley (ley@uni-trier.de)
