VTS 2006:
Berkeley,
CA,
USA
24th IEEE VLSI Test Symposium (VTS 2006), 30 April - 4 May 2006, Berkeley, California, USA.
IEEE Computer Society 2006, ISBN 0-7695-2514-8 BibTeX
Introduction
Session 1A:
Delay Testing I
Session 1B:
High Speed Interconnect Test
Session 1C - IP Session:
Reliability Screening Methods for High-Performance Processors in Advanced Technologies
Session 2A:
Heat and Power Issues in Test
- Chunsheng Liu, Vikram Iyengar, Dhiraj K. Pradhan:
Thermal-Aware Testing of Network-on-Chip Using Multiple-Frequency Clocking.
46-51
Electronic Edition (link) BibTeX
- Minsik Cho, David Z. Pan:
PEAKASO: Peak-Temperature Aware Scan-Vector Optimization.
52-57
Electronic Edition (link) BibTeX
- Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Tatsuya Suzuki, Kewal K. Saluja, Laung-Terng Wang, Khader S. Abdel-Hafez, Kozo Kinoshita:
A New ATPG Method for Efficient Capture Power Reduction During Scan Testing.
58-65
Electronic Edition (link) BibTeX
Session 2B:
Test Quality
Session 2C - IP Session:
Scan Compression:
Techniques,
Tradeoffs and Entitlement
Session 3A:
IP Protection and Interconnect Testing
Session 3B:
Flash and Memory Testing
- O. Ginez, Jean Michel Daga, Marylene Combe, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
An Overview of Failure Mechanisms in Embedded Flash Memories.
108-113
Electronic Edition (link) BibTeX
- Yu-Ying Hsiao, Chao-Hsun Chen, Cheng-Wen Wu:
A Built-In Self-Repair Scheme for NOR-Type Flash Memory.
114-119
Electronic Edition (link) BibTeX
- Gurgen Harutunyan, Valery A. Vardanian, Y. Zorian Zorian:
Minimal March Test Algorithm for Detection of Linked Static Faults in Random Access Memories.
120-127
Electronic Edition (link) BibTeX
Session 3C - IP Session:
Nanometer IC Testing:
Perspective from Foundries
Session 4A:
Yield Analysis
Session 4B - New Topic Session:
Emerging Nanoelectronic Devices for High-Speed,
Low-Power Applications
Session 4C - IP Session:
TRP in Action:
Embedded Instrumentation in FPGAs
Session 5A:
- Special Session:
The Future of DFT Sector:
Point Tools or Integrated Solutions
Session 5B - Special Session:
Elevator Talks
Session 5C - Embedded Tutorial:
Functional ATPG
Session 6A:
Test Generation and Test Flows
- Vlado Vorisek, Bruce Swanson, Kun-Han Tsai, Dhiraj Goswami:
Improved Handling of False and Multicycle Paths in ATPG.
160-165
Electronic Edition (link) BibTeX
- Davide Appello, Vincenzo Tancorre, Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda:
On the Automation of the Test Flow of Complex SoCs.
166-171
Electronic Edition (link) BibTeX
- Giuseppe Di Guglielmo, Franco Fummi, Cristina Marconcini, Graziano Pravadelli:
Improving Gate-Level ATPG by Traversing Concurrent EFSMs.
172-179
Electronic Edition (link) BibTeX
Session 6B:
IDDQ,
MEMS,
and Wireless Testing
Session 6C - IP Session:
Test Strategies of Leading Edge SoCs
Session 7A:
Designing Robust CMOS and Nanoelectronics
Session 7B:
RF Testing
Session 7C - IP Sessin:
High Test Parallelism,
Throughput and Quality at a Low Cost:
Which Test Cells and Which Partitioning of Test Resources Can Enable All This?
Session 8A:
Test Size Reductions
Session 8B:
Transistor Level Diagnosis
Session 8C - IP Session:
Soft Error Impact on Modern Systems
Session 9A - Panel Session:
Real-Time Volume Diagnostics:
Requirements and Challenges
Session 9B - Special Sesion:
Doctoral Thesis Award
Session 9C - Panel Session:
Three Questions to Oracle
Session 10A:
Delay Testing II
Session 10B:
Analog Test
Session 10C - IP Session:
System-in-Package Design and Test Practices
Session 11A:
Delay Testing III
Session 11B:
Nanoscale Testing
Session 11C - IP Session:
Impact of Variations on Designs and Test
Session 12A:
Scan Based Diagnosis
Session 12B:
Mixed Signal Test
Session 12C - IP Session:
Making the (Yield) Difference:
DFY/DFM
Session 13A:
Embedded Tutorial:
Silicon Debug Challenges for Nanometer Designs
Session 13B - Hot Topic Session:
Signal Integrity:
How Can It be Designed into Multiprocessor Platforms,
Systems On-Chip,
and Systems in-Package?
Session 13C - Panel Session:
Changing Role of Test:
Is ATE Ready?
Copyright © Sat May 16 23:47:01 2009
by Michael Ley (ley@uni-trier.de)
