| 2008 |
|---|
| 6 | EE | Santiago Remersaro,
Janusz Rajski,
Thomas Rinderknecht,
Sudhakar M. Reddy,
Irith Pomeranz:
ATPG Heuristics Dependant Observation Point Insertion for Enhanced Compaction and Data Volume Reduction.
DFT 2008: 385-393 |
| 2005 |
|---|
| 5 | EE | Liyang Lai,
Janak H. Patel,
Thomas Rinderknecht,
Wu-Tung Cheng:
Hardware Ef.cient LBISTWith Complementary Weights.
ICCD 2005: 479-484 |
| 2004 |
|---|
| 4 | EE | Liyang Lai,
Janak H. Patel,
Thomas Rinderknecht,
Wu-Tung Cheng:
Logic BIST with Scan Chain Segmentation.
ITC 2004: 57-66 |
| 3 | EE | Janusz Rajski,
Nilanjan Mukherjee,
Jerzy Tyszer,
Thomas Rinderknecht:
Embedded Test for Low Cost Manufacturing.
VLSI Design 2004: 21-23 |
| 2 | EE | Liyang Lai,
Thomas Rinderknecht,
Wu-Tung Cheng,
Janak H. Patel:
Logic BIST Using Constrained Scan Cells.
VTS 2004: 199-205 |
| 2003 |
|---|
| 1 | EE | Xijiang Lin,
Ron Press,
Janusz Rajski,
Paul Reuter,
Thomas Rinderknecht,
Bruce Swanson,
Nagesh Tamarapalli:
High-Frequency, At-Speed Scan Testing.
IEEE Design & Test of Computers 20(5): 17-25 (2003) |
