Volume 14,
Number 1,
January 1995
- Werner Geurts, Francky Catthoor, Hugo De Man:
Quadratic zero-one programming-based synthesis of application-specific data paths.
1-11
Electronic Edition (link) BibTeX
- Anantha P. Chandrakasan, Miodrag Potkonjak, Renu Mehra, Jan M. Rabaey, Robert W. Brodersen:
Optimizing power using transformations.
12-31
Electronic Edition (link) BibTeX
- William K. C. Lam, Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Delay fault coverage, test set size, and performance trade-offs.
32-44
Electronic Edition (link) BibTeX
- Luciano Lavagno, Cho W. Moon, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
An efficient heuristic procedure for solving the state assignment problem for event-based specifications.
45-60
Electronic Edition (link) BibTeX
- Luciano Lavagno, Kurt Keutzer, Alberto L. Sangiovanni-Vincentelli:
Synthesis of hazard-free asynchronous circuits with bounded wire delays.
61-86
Electronic Edition (link) BibTeX
- Amelia Shen, Srinivas Devadas, Abhijit Ghosh:
Probabilistic manipulation of Boolean functions using free Boolean diagrams.
87-95
Electronic Edition (link) BibTeX
- L. James Hwang, Abbas El Gamal:
Min-cut replication in partitioned networks.
96-106
Electronic Edition (link) BibTeX
- Enrico Malavasi, Davide Pandini:
Optimum CMOS stack generation with analog constraints.
107-122
Electronic Edition (link) BibTeX
- Peichen Pan, C. L. Liu:
Area minimization for floorplans.
123-132
Electronic Edition (link) BibTeX
Volume 14,
Number 2,
February 1995
- Mariusz Niewczas, Adam Wojtasik:
Modeling of VLSI RC parasitics based on the network reduction algorithm.
137-144
Electronic Edition (link) BibTeX
- Ching-Wei Yeh, Chung-Kuan Cheng, Ting-Ting Y. Lin:
Optimization by iterative improvement: an experimental evaluation on two-way partitioning.
145-153
Electronic Edition (link) BibTeX
- Ching-Wei Yeh, Chung-Kuan Cheng, Ting-Ting Y. Lin:
Circuit clustering using a stochastic flow injection method.
154-162
Electronic Edition (link) BibTeX
- Benjamín Iñíguez, Eugenio García Moreno:
Development of a Cinfinity-continuous small-signal model for a MOS transistor in normal operation.
163-166
Electronic Edition (link) BibTeX
- Zhixin Yan, M. Jamal Deen:
New RTD large-signal DC model suitable for PSPICE.
167-172
Electronic Edition (link) BibTeX
- Chun-Jung Chen, Wu-Shiung Feng:
Relaxation-based transient sensitivity computations for MOSFET circuits.
173-185
Electronic Edition (link) BibTeX
- Eli Chiprout, Michel S. Nakhla:
Analysis of interconnect networks using complex frequency hopping (CFH).
186-200
Electronic Edition (link) BibTeX
- Chen-Liang Fang, Wen-Ben Jone:
Timing optimization by gate resizing and critical path identification.
201-217
Electronic Edition (link) BibTeX
- Christofer Toumazou, Costas A. Makris:
Analog IC design automation. I. Automated circuit generation: new concepts and methods.
218-238
Electronic Edition (link) BibTeX
- Costas A. Makris, Christofer Toumazou:
Analog IC design automation. II. Automated circuit correction by qualitative reasoning.
239-254
Electronic Edition (link) BibTeX
- Irith Pomeranz, Sudhakar M. Reddy:
On correction of multiple design errors.
255-264
Electronic Edition (link) BibTeX
- Ting-Chi Wang, Martin D. F. Wong, Yachyang Sun, Chak-Kuen Wong:
Optimal net assignment.
265-269
Electronic Edition (link) BibTeX
Volume 14,
Number 3,
March 1995
- Ching-Yi Wang, Keshab K. Parhi:
High-level DSP synthesis using concurrent transformations, scheduling, and allocation.
274-295
Electronic Edition (link) BibTeX
- Moon-Jung Chung, Sangchul Kim:
A path-oriented algorithm for the cell selection problem.
296-307
Electronic Edition (link) BibTeX
- Weitong Chuang, Sachin S. Sapatnekar, Ibrahim N. Hajj:
Timing and area optimization for standard-cell VLSI circuit design.
308-320
Electronic Edition (link) BibTeX
- Jason Cong, Kwok-Shing Leung:
Optimal wiresizing under Elmore delay model.
321-336
Electronic Edition (link) BibTeX
- Wen-Chung Kao, Tai-Ming Parng:
Cross point assignment with global rerouting for general-architecture designs.
337-348
Electronic Edition (link) BibTeX
- Wern-Jieh Sun, Carl Sechen:
Efficient and effective placement for very large circuits.
349-359
Electronic Edition (link) BibTeX
- Michael M. Green, Alan N. Willson Jr.:
An algorithm for identifying unstable operating points using SPICE.
360-370
Electronic Edition (link) BibTeX
- Ching-Dong Chen, Yuh-Sheng Lee, Allen C.-H. Wu, Youn-Long Lin:
TRACER-fpga: a router for RAM-based FPGA's.
371-374
Electronic Edition (link) BibTeX
- Wen-Ben Jone, Christos A. Papachristou:
A coordinated circuit partitioning and test generation method for pseudo-exhaustive testing of VLSI circuits.
374-384
Electronic Edition (link) BibTeX
- Ayman I. Kayssi, Karem A. Sakallah:
Timing models for gallium arsenide direct-coupled FET logic circuits.
384-393
Electronic Edition (link) BibTeX
- Yu-Wen Tsay, Youn-Long Lin:
A row-based cell placement method that utilizes circuit structural properties.
393-397
Electronic Edition (link) BibTeX
Volume 14,
Number 4,
April 1995
- Prabir C. Maulik, L. Richard Carley, Rob A. Rutenbar:
Integer programming based topology selection of cell-level analog circuits.
401-412
Electronic Edition (link) BibTeX
- Scott Hazelhurst, Carl-Johan H. Seger:
A simple theorem prover based on symbolic trajectory evaluation and BDD's.
413-422
Electronic Edition (link) BibTeX
- Malgorzata Marek-Sadowska, Majid Sarrafzadeh:
The crossing distribution problem [IC layout].
423-433
Electronic Edition (link) BibTeX
- Kazuhiro Takahashi, Kazuo Nakajima, Masayuki Terai, Koji Sato:
Min-cut placement with global objective functions for large scale sea-of-gates arrays.
434-446
Electronic Edition (link) BibTeX
- Abhijit Dharchoudhury, Sung-Mo Kang:
Worst-case analysis and optimization of VLSI circuit performances.
481-492
Electronic Edition (link) BibTeX
- Michael S. Obrecht, Mohamed I. Elmasry, Edwin L. Heasell:
TRASIM: compact and efficient two-dimensional transient simulator for arbitrary planar semiconductor devices.
447-458
Electronic Edition (link) BibTeX
- Jacco L. Pleumeekers, Claude M. Simon, Serge Mottet:
Investigation into the properties of the explicit method for the resolution of the semiconductor device equations.
459-463
Electronic Edition (link) BibTeX
- Asim Salim, Tajinder Manku, Arokia Nathan:
Modeling of magnetic field sensitivity of bipolar magnetotransistors using HSPICE.
464-469
Electronic Edition (link) BibTeX
- Umakanta Choudhury, Alberto L. Sangiovanni-Vincentelli:
Automatic generation of analytical models for interconnect capacitances.
470-480
Electronic Edition (link) BibTeX
- Edward W. Y. Liu, Alberto L. Sangiovanni-Vincentelli:
Verification of Nyquist data converters using behavioral simulation.
493-502
Electronic Edition (link) BibTeX
- Timothy Kam, P. A. Subrahmanyam:
Comparing layouts with HDL models: a formal verification technique.
503-509
Electronic Edition (link) BibTeX
- Wen Fang, M. Ebrahim Mokari-Bolhassan, David Smart:
Robust VLSI circuit simulation techniques based on overlapped waveform relaxation.
510-518
Electronic Edition (link) BibTeX
- Wing Ning Li:
The complexity of segmented channel routing.
518-523
Electronic Edition (link) BibTeX
- So-Zen Yao, Chung-Kuan Cheng, Debaprosad Dutt, Surendra Nahar, Chi-Yuan Lo:
A cell-based hierarchical pitchmatching compaction using minimal LP.
523-526
Electronic Edition (link) BibTeX
Volume 14,
Number 5,
May 1995
- Miodrag Potkonjak, Sujit Dey, Rabindra K. Roy:
Considering testability at behavioral level: use of transformations for partial scan cost minimization under timing and area constraints.
531-546
Electronic Edition (link) BibTeX
- Steffen Tarnick:
Controllable self-checking checkers for conditional concurrent checking.
547-553
Electronic Edition (link) BibTeX
- Mody Lempel, Sandeep K. Gupta, Melvin A. Breuer:
Test embedding with discrete logarithms.
554-566
Electronic Edition (link) BibTeX
- Siyad C. Ma, Edward J. McCluskey:
Open faults in BiCMOS gates.
567-575
Electronic Edition (link) BibTeX
- Wuudiann Ke, Premachandran R. Menon:
Path-delay-fault testable nonscan sequential circuits.
576-582
Electronic Edition (link) BibTeX
- Aiman H. El-Maleh, Janusz Rajski:
Delay-fault testability preservation of the concurrent decomposition and factorization transformations.
582-590
Electronic Edition (link) BibTeX
- Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell:
Fault coverage estimation by test vector sampling.
590-596
Electronic Edition (link) BibTeX
- Terry Lee, Weitong Chuang, Ibrahim N. Hajj, W. Kent Fuchs:
Circuit-level dictionaries of CMOS bridging faults.
596-603
Electronic Edition (link) BibTeX
- Peter C. Maxwell:
Reductions in quality caused by uneven fault coverage of different areas of an integrated circuit.
603-607
Electronic Edition (link) BibTeX
- Vladimir Kolarik, Salvador Mir, Marcelo Lubaszewski, Bernard Courtois:
Analog checkers with absolute and relative tolerances.
607-612
Electronic Edition (link) BibTeX
- Yanbing Xu, Mostafa H. Abd-El-Barr, Carl McCrosky:
Graph-based output phase assignment for PLA minimization.
613-622
Electronic Edition (link) BibTeX
- Lung-Tien Liu, Ming-Ter Kuo, Chung-Kuan Cheng, T. C. Hu:
A replication cut for two-way partitioning.
623-630
Electronic Edition (link) BibTeX
- Masato Fujinaga, I. Tottori, Tatsuya Kunikiyo, Tetsuya Uchida, Norihiko Kotani, Yasumasa Tsukamoto:
3-D numerical modeling of thermal flow for insulating thin film using surface diffusion.
631-638
Electronic Edition (link) BibTeX
- Peter Feldmann, Roland W. Freund:
Efficient linear circuit analysis by Pade approximation via the Lanczos process.
639-649
Electronic Edition (link) BibTeX
Volume 14,
Number 6,
June 1995
- Sundarar Mohan, Jian Ping Sun, Pinaki Mazumder, George I. Haddad:
Device and circuit simulation of quantum electronic devices.
653-662
Electronic Edition (link) BibTeX
- Ing-Jer Huang, Alvin M. Despain:
Synthesis of application specific instruction sets.
663-675
Electronic Edition (link) BibTeX
- Mani B. Srivastava, Robert W. Brodersen:
SIERA: a unified framework for rapid-prototyping of system-level hardware and software.
676-693
Electronic Edition (link) BibTeX
- Frank Vahid, Sanjiv Narayan, Daniel D. Gajski:
SpecCharts: a VHDL front-end for embedded systems.
694-706
Electronic Edition (link) BibTeX
- Akira Onozawa, Kamal Chaudhary, Ernest S. Kuh:
Performance driven spacing algorithms using attractive and repulsive constraints for submicron LSI's.
707-719
Electronic Edition (link) BibTeX
- Karl Michael Eickhoff, Walter L. Engl:
Levelized incomplete LU factorization and its application to large-scale circuit simulation.
720-727
Electronic Edition (link) BibTeX
- Srimat T. Chakradhar, Mahesh A. Iyer, Vishwani D. Agrawal:
Energy models for delay testing.
728-739
Electronic Edition (link) BibTeX
- Yih-Lang Li, Cheng-Wen Wu:
Cellular automata for efficient parallel logic and fault simulation.
740-749
Electronic Edition (link) BibTeX
- Sridhar Narayanan, Melvin A. Breuer:
Reconfiguration techniques for a single scan chain.
750-765
Electronic Edition (link) BibTeX
- T. W. Her, Martin D. F. Wong:
On over-the-cell channel routing with cell orientations consideration.
766-772
Electronic Edition (link) BibTeX
- Wuudiann Ke, Premachandran R. Menon:
Delay-testable implementations of symmetric functions.
772-775
Electronic Edition (link) BibTeX
- Venkat Thanvantri, Sartaj Sahni:
Folding a stack of equal width components.
775-780
Electronic Edition (link) BibTeX
- Bernard A. McCoy, Gabriel Robins:
Non-tree routing [VLSI layout].
780-784
Electronic Edition (link) BibTeX
Volume 14,
Number 7,
July 1995
- Mounir Fares, Bozena Kaminska:
FPAD: a fuzzy nonlinear programming approach to analog circuit design.
785-793
Electronic Edition (link) BibTeX
- Julie Chen, Andrew T. Yang:
STYLE: a statistical design approach based on nonparametric performance macromodeling.
794-802
Electronic Edition (link) BibTeX
- G. Hari Rama Krishna, Amit K. Aditya, Nirmal B. Chakrabarti, Swapna Banerjee:
Finite element analysis of SiGe heterojunction devices.
803-814
Electronic Edition (link) BibTeX
- Yevgeny V. Mamontov, Magnus Willander:
Accounting thermal noise in mathematical models of quasi-homogeneous regions in silicon devices.
815-823
Electronic Edition (link) BibTeX
- Shinji Odanaka, Tatsuo Nogi:
Massively parallel computation using a splitting-up operator method for three-dimensional device simulation.
824-832
Electronic Edition (link) BibTeX
- S. C. Leung, Hon F. Li:
On the realizability and synthesis of delay-insensitive behaviors.
833-848
Electronic Edition (link) BibTeX
- T. W. Her, Ting-Chi Wang, Martin D. F. Wong:
Performance-driven channel pin assignment algorithms.
849-857
Electronic Edition (link) BibTeX
- M. Helena Fino, José E. da Franca, Adolfo Steiger-Garção:
Automatic symbolic analysis of switched-capacitor filtering networks using signal flow graphs.
858-867
Electronic Edition (link) BibTeX
- Jeong-Taek Kong, David Overhauser:
Methods to improve digital MOS macromodel accuracy.
868-881
Electronic Edition (link) BibTeX
- Jeffrey R. Parkhurst, Lawrence L. Ogborn:
Determining the steady-state output of nonlinear oscillatory circuits using multiple shooting.
882-889
Electronic Edition (link) BibTeX
- Charles J. Alpert, T. C. Hu, Dennis J.-H. Huang, Andrew B. Kahng, David R. Karger:
Prim-Dijkstra tradeoffs for improved performance-driven routing tree design.
890-896
Electronic Edition (link) BibTeX
- C. Y. Roger Chen, Cliff Yungchin Hou, Bradley S. Carlson:
A preprocessor for improving channel routing hierarchical pin permutation.
896-903
Electronic Edition (link) BibTeX
- Seonghun Cho, Sartaj Sahni:
Minimum area joining of compacted cells.
903-909
Electronic Edition (link) BibTeX
- Luis Entrena-Arrontes, Kwang-Ting Cheng:
Combinational and sequential logic optimization by redundancy addition and removal.
909-916
Electronic Edition (link) BibTeX
Volume 14,
Number 8,
August 1995
- Joseph W. Jerome, Chi-Wang Shu:
Transport effects and characteristic modes in the modeling and simulation of submicron devices.
917-923
Electronic Edition (link) BibTeX
- Mark G. Graham, John J. Paulos, Douglas W. Nychka:
Template-based MOSFET device model.
924-933
Electronic Edition (link) BibTeX
- Muhammad K. Dhodhi, Frank H. Hielscher, Robert H. Storer, Jayaram Bhasker:
Datapath synthesis using a problem-space genetic algorithm.
934-944
Electronic Edition (link) BibTeX
- Wim F. J. Verhaegh, Paul E. R. Lippens, Emile H. L. Aarts, Jan H. M. Korst, Jef L. van Meerbergen, Albert van der Werf:
Improved force-directed scheduling in high-throughput digital signal processing.
945-960
Electronic Edition (link) BibTeX
- Jun Gu, Ruchir Puri:
Asynchronous circuit synthesis with Boolean satisfiability.
961-973
Electronic Edition (link) BibTeX
- Bill Lin, Srinivas Devadas:
Synthesis of hazard-free multilevel logic under multiple-input changes from binary decision diagrams.
974-985
Electronic Edition (link) BibTeX
- Steven M. Nowick, David L. Dill:
Exact two-level minimization of hazard-free logic with multiple-input changes.
986-997
Electronic Edition (link) BibTeX
- Harish Kriplani, Farid N. Najm, Ibrahim N. Hajj:
Pattern independent maximum current estimation in power and ground buses of CMOS VLSI circuits: Algorithms, signal correlations, and their resolution.
998-1012
Electronic Edition (link) BibTeX
- Mysore Sriram, Sung-Mo Kang:
Efficient approximation of the time domain response of lossy coupled transmission line trees.
1013-1024
Electronic Edition (link) BibTeX
- Pranav Ashar, Sharad Malik:
Functional timing analysis using ATPG.
1025-1030
Electronic Edition (link) BibTeX
- D. Lambidonis, André Ivanov, Vinod K. Agarwal:
Fast signature computation for BIST linear compactors.
1037-1044
Electronic Edition (link) BibTeX
- Slawomir Pilarski:
Comments on "Test efficiency analysis of random self-test of sequential circuits".
1044-1045
Electronic Edition (link) BibTeX
- C. Y. Roger Chen, Cliff Yungchin Hou:
A pin permutation algorithm for improving over-the-cell channel routing.
1030-1037
Electronic Edition (link) BibTeX
Volume 14,
Number 9,
September 1995
- Ming-Huei Shieh, Hung Chang Lin:
Modeling hysteretic current-voltage characteristics for resonant tunneling diodes.
1098-1103
Electronic Edition (link) BibTeX
- Bernd Becker, Rolf Drechsler, Paul Molitor:
On the generation of area-time optimal testable adders.
1049-1066
Electronic Edition (link) BibTeX
- Pranav Ashar, Sujit Dey, Sharad Malik:
Exploiting multicycle false paths in the performance optimization of sequential logic circuits.
1067-1075
Electronic Edition (link) BibTeX
- Chau-Shen Chen, Yu-Wen Tsay, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin:
Combining technology mapping and placement for delay-minimization in FPGA designs.
1076-1084
Electronic Edition (link) BibTeX
- Nan-Chi Chou, Lung-Tien Liu, Chung-Kuan Cheng, Wei-Jin Dai, Rodney Lindelof:
Local ratio cut and set covering partitioning for huge logic emulation systems.
1085-1092
Electronic Edition (link) BibTeX
- Akira Ito:
A voltage dependent capacitance model including effects of manufacturing process variabilities on voltage coefficients.
1093-1097
Electronic Edition (link) BibTeX
- Ernst Strasser, Siegfried Selberherr:
Algorithms and models for cellular based topography simulation.
1104-1114
Electronic Edition (link) BibTeX
- Suman Kanjilal, Srimat T. Chakradhar, Vishwani D. Agrawal:
Test function embedding algorithms with application to interconnected finite state machines.
1115-1127
Electronic Edition (link) BibTeX
- Soo Young Lee, Kewal K. Saluja:
Test application time reduction for sequential circuits with scan.
1128-1140
Electronic Edition (link) BibTeX
- Miodrag Potkonjak, Sujit Dey, Rabindra K. Roy:
Behavioral synthesis of area-efficient testable designs using interaction between hardware sharing and partial scan.
1141-1154
Electronic Edition (link) BibTeX
- Vishwani D. Agrawal, Srimat T. Chakradhar:
Combinational ATPG theorems for identifying untestable faults in sequential circuits.
1155-1160
Electronic Edition (link) BibTeX
- Dimitrios Kagaris, Spyros Tragoudas, Dinesh Bhatia:
Pseudo-exhaustive built-in TPG for sequential circuits.
1160-1171
Electronic Edition (link) BibTeX
- Vijay Raghavendra, Chidchanok Lursinsap:
A technique for micro-rollback self-recovery synthesis.
1171-1179
Electronic Edition (link) BibTeX
Volume 14,
Number 10,
October 1995
- Bradley S. Carlson, Suh-Juch Lee:
Delay optimization of digital CMOS VLSI circuits by transistor reordering.
1183-1192
Electronic Edition (link) BibTeX
- Abhijit Chatterjee, Charles F. Machala III, Ping Yang:
A submicron DC MOSFET model for simulation of analog circuits.
1193-1207
Electronic Edition (link) BibTeX
- Stefan Halama, Christoph Pichler, Gerhard Rieger, Gerhard Schrom, Thomas Simlinger, Siegfried Selberherr:
VISTA-user interface, task level, and tool integration.
1208-1222
Electronic Edition (link) BibTeX
- Mark E. Law:
Grid adaption near moving boundaries in two dimensions for IC process simulation.
1223-1230
Electronic Edition (link) BibTeX
- Alfred Kwok Kit Wong, Roberto Guerrieri, Andrew R. Neureuther:
Massively parallel electromagnetic simulation for photolithographic applications.
1231-1240
Electronic Edition (link) BibTeX
- Wolfgang Meyer, Raul Camposano:
Active timing multilevel fault-simulation with switch-level accuracy.
1241-1256
Electronic Edition (link) BibTeX
- Jay B. Brockman, Stephen W. Director:
The schema-based approach to workflow management.
1257-1267
Electronic Edition (link) BibTeX
- Suman Kanjilal, Srimat T. Chakradhar, Vishwani D. Agrawal:
A partition and resynthesis approach to testable design of large circuits.
1268-1276
Electronic Edition (link) BibTeX
- Kei-Yong Khoo, Jason Cong:
An efficient multilayer MCM router based on four-via routing.
1277-1290
Electronic Edition (link) BibTeX
- Chin-Long Wey, Shoba Krishnan, Sondes Sahli:
Test generation and concurrent error detection in current-mode A/D converters.
1291-1298
Electronic Edition (link) BibTeX
- Miquel Roca, Antonio Rubio:
Current testability analysis of feedback bridging faults in CMOS circuits.
1299-1305
Electronic Edition (link) BibTeX
- Ching-Wei Yeh:
On the acceleration of flow-oriented circuit clustering.
1305-1308
Electronic Edition (link) BibTeX
Volume 14,
Number 11,
November 1995
- Ting-Wei Tang, Mei-Kei Ieong:
Discretization of flux densities in device simulations using optimum artificial diffusivity.
1309-1315
Electronic Edition (link) BibTeX
- Maurizio Damiani, Jerry Chih-Yuan Yang, Giovanni De Micheli:
Optimization of combinational logic circuits based on compatible gates.
1316-1327
Electronic Edition (link) BibTeX
- Mitchell A. Thornton, V. S. S. Nair:
Efficient calculation of spectral coefficients and their applications.
1328-1341
Electronic Edition (link) BibTeX
- Charles J. Alpert, Andrew B. Kahng:
Multiway partitioning via geometric embeddings, orderings, and dynamic programming.
1342-1358
Electronic Edition (link) BibTeX
- Qinghong Wu, C. Y. Roger Chen, Bradley S. Carlson:
LILA: layout generation for iterative logic arrays.
1359-1369
Electronic Edition (link) BibTeX
- Jau-Shien Chang, Chen-Shang Lin:
Test set compaction for combinational circuits.
1370-1378
Electronic Edition (link) BibTeX
- Murali M. R. Gala, Don E. Ross, Karan L. Watson, Beena Vasudevan, Peter Utama:
Built-in self test for C-testable ILA's.
1388-1398
Electronic Edition (link) BibTeX
- Jien-Chung Lo, James C. Daly, Michael Nicolaidis:
A strongly code disjoint built-in current sensor for strongly fault-secure static CMOS realizations.
1402-1407
Electronic Edition (link) BibTeX
- Anand Raghunathan, Pranav Ashar, Sharad Malik:
Test generation for cyclic combinational circuits.
1408-1414
Electronic Edition (link) BibTeX
- Owen Kaser:
On squashing hierarchical designs [VLSI].
1398-1402
Electronic Edition (link) BibTeX
- Jacob Savir:
Shrinking wide compressors [BIST].
1379-1387
Electronic Edition (link) BibTeX
Volume 14,
Number 12,
December 1995
- Kenneth D. Boese, Andrew B. Kahng, Bernard A. McCoy, Gabriel Robins:
Near-optimal critical sink routing tree constructions.
1417-1436
Electronic Edition (link) BibTeX
- Steven Bova, Graham F. Carey:
A Taylor-Galerkin finite element method for the hydrodynamic semiconductor equations.
1437-1444
Electronic Edition (link) BibTeX
- Kuen-Jong Lee, Chih-Nan Wang, Rajiv Gupta, Melvin A. Breuer:
An integrated system for assigning signal flow directions to CMOS transistors.
1445-1458
Electronic Edition (link) BibTeX
- Ivan L. Wemple, Andrew T. Yang:
Integrated circuit substrate coupling models based on Voronoi tessellation.
1459-1469
Electronic Edition (link) BibTeX
- K. Fuchs:
Synthesis for path delay fault testability via tautology-based untestability identification and factorization.
1470-1479
Electronic Edition (link) BibTeX
- Kamal Chaudhary, Massoud Pedram:
Computing the area versus delay trade-off curves in technology mapping.
1480-1489
Electronic Edition (link) BibTeX
- Rajmohan Rajaraman, Martin D. F. Wong:
Optimum clustering for delay minimization.
1490-1495
Electronic Edition (link) BibTeX
- Seiji Kajihara, Irith Pomeranz, Kozo Kinoshita, Sudhakar M. Reddy:
Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits.
1496-1504
Electronic Edition (link) BibTeX
- Irith Pomeranz, Sudhakar M. Reddy, Prasanti Uppaluri:
NEST: a nonenumerative test generation method for path delay faults in combinational circuits.
1505-1515
Electronic Edition (link) BibTeX
- Ted Stanion, Debashis Bhattacharya, Carl Sechen:
An efficient method for generating exhaustive test sets.
1516-1525
Electronic Edition (link) BibTeX
- Chuan-Hua Chang, Edward S. Davidson, Karem A. Sakallah:
Maximum rate single-phase clocking of a closed pipeline including wave pipelining, stoppability, and startability.
1526-1545
Electronic Edition (link) BibTeX
- Elizabeth J. Brauer, Sung-Mo Kang:
An algorithm for functional verification of digital ECL circuits.
1546-1556
Electronic Edition (link) BibTeX
- Kannan Krishna, Stephen W. Director:
The linearized performance penalty (LPP) method for optimization of parametric yield and its reliability.
1557-1568
Electronic Edition (link) BibTeX
- Kurt Keutzer, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli:
Synthesis for testability techniques for asynchronous circuits.
1569-1577
Electronic Edition (link) BibTeX
- Dhiraj K. Pradhan, Jayashree Saxena:
A novel scheme to reduce test application time in circuits with full scan.
1577-1586
Electronic Edition (link) BibTeX
- Alexander Y. Tetelbaum:
Generalized optimum path search.
1586-1590
Electronic Edition (link) BibTeX
Copyright © Sun May 17 00:23:11 2009
by Michael Ley (ley@uni-trier.de)