VLSI-SoC 2003:
Darmstadt,
Germany
Manfred Glesner, Ricardo Augusto da Luz Reis, Hans Eveking, Vincent John Mooney III, Leandro Soares Indrusiak, Peter Zipf (Eds.):
IFIP VLSI-SoC 2003, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Darmstadt, Germany, 1-3 December 2003.
Technische Universität Darmstadt, Insitute of Microelectronic Systems 2003, ISBN 3-901882-17-0 BibTeX
Copies of these proceedings may be ordered from:
Technische Universität Darmstadt
Institute of Microelectronic Systems
Karlstr. 15, D-64283 Darmstadt,
Germany
vlsi2003@mes.tu-darmstadt.de
http:
//www.microelectronic.e-technik.tu-darmstadt.de
Phone:
+49 6151 165136
Fax:
+49 6151 164936
Keynotes
Tutorials
Modeling Parasitic Effects on VLSI SoC
Synthesis and Communication
- Philippe Coussy, Adel Baganne, Eric Martin:
Communication and Timing Constraints Analysis for IP Design and Integration.
38-43 BibTeX
- Thomas Hollstein, Ralf Ludewig, Christoph Mager, Peter Zipf, Manfred Glesner:
A hierarchical generic approach for on-chip communication, testing and debugging of SoCs.
44-49 BibTeX
- Maciej Borkowski, Juha Häkkinen, Juha Kostamovaara:
A Sigma-Delta Modulator Development Environment for Fractional-N Frequency Synthesis.
50-54 BibTeX
- Axel G. Braun, Jan B. Freuer, Joachim Gerlach, Wolfgang Rosenstiel:
Automated Conversion of SystemC Fixed-Point Data Types for Hardware Synthesis.
55- BibTeX
Novel Architectures
Verification
Architecture Customization Techniques
- Arkadiy Morgenshtein, Michael Moreinis, Israel A. Wagner, Avinoam Kolodny:
Logic Gates as Repeaters (LGR) for Timing Optimization of SoC Interconnects.
99-104 BibTeX
- Marios Kesoulis, Dimitrios Soudris, C. Koukourlis, Adonios Thanailakis:
Designing Low Power Direct Digital Frequency Synthesizers.
105-110 BibTeX
- José Augusto Miranda Nacif, Flávio Miana de Paula, Harry Foster, Claudionor José Nunes Coelho Jr., Antônio Otávio Fernandes:
The Chip is Ready. Am I done? On-chip Verification using Assertion Processors.
111- BibTeX
Fine-Grained Reconfigurable Platforms
Mixed Signal Circuits
Mobile and Multimedia Reconfigurable Computing
- Péter Szántó, Béla Fehér:
3D rendering using FPGAs.
149-154 BibTeX
- Hans-Joachim Stolberg, Mladen Berekovic, Lars Friebe, Sören Moch, Mark Bernd Kulaczewski, Peter Pirsch:
HiBRID-SoC: A Multi-Core System-on-Chip Architecture for Multimedia Signal Processing.
155-160 BibTeX
- Thilo Pionteck, Lukusa D. Kabulepa, Manfred Glesner:
Exploring the Capabilities of Reconfigurable Hardware for OFDM-based WLANs.
161-166 BibTeX
- Mihail Petrov, Abdulfattah Mohammad Obeid, Tudor Murgan, Peter Zipf, Jörg Brakensiek, Bernard Ölkrug, Manfred Glesner:
An Adaptive Trace-Back Solution for State-Parallel Viterbi Decoders.
167- BibTeX
Test for SoC IP Cores
SoC Physical Layout Techniques
Test Circuits and Systems
Processor and IP Design
Novel Circuit Techniques for Ultra Low Power SoC
Coarse-Grained Reconfigurable Architectures
Signal Processing IP Blocks
SoC Design
- Zahid Khan, Tughrul Arslan, Ahmet T. Erdogan:
Crosstalk Immune Coding from Area and Power Perspective for high performance AMBA based SoC systems.
314-317 BibTeX
- Fernando Gehm Moraes, Aline Mello, Leandro Möller, Luciano Ost, Ney Laert Vilar Calazans:
A Low Area Overhead Packet-switched Network on Chip: Architecture and Prototyping.
318-323 BibTeX
- Michael S. McCorquodale, Eric D. Marsman, Robert M. Senger, Fadi H. Gebara, Richard B. Brown:
Microsystem and SoC Design with UMIPS.
324- BibTeX
Gate-level Testing
Advanced IP Cores
- Juan Manuel García Chamizo, Jerónimo Mora Pascual, Higinio Mora Mora, Maria Teresa Signes Pont:
Calculation Methodology for Flexible Arithmetic Processing.
350-355 BibTeX
- Radu Dogaru, Cristian Chitu, Manfred Glesner:
A Versatile Cellular Neural Circuit Based on a Multi-nested Approach: Functional Capabilities and Applications.
356-361 BibTeX
- Dinesh Pamunuwa, Johnny Öberg, Li-Rong Zheng, Mikael Millberg, Axel Jantsch:
Layout, Performance and Power Trade-Offs in Mesh-Based Network-on-Chip Architectures.
362- BibTeX
Poster Session
- Shrutin Ulman:
Delay and Short Circuit Power Estimation for a Submicron CMOS Inverter driving a CRC-PI Interconnect Load.
369-374 BibTeX
- Martin Margala, Quentin Diduck, Eric Moule:
1.8V 0.18µm CMOS Novel Successive Approximation ADC.
375-379 BibTeX
- Martin Margala, John Liobe, Quentin Diduck:
Deep-Submicron CMOS Design Methodology for High-Performance Low-Power Analog-to-Digital Converters.
380-385 BibTeX
- Martin Margala, Magdy A. El-Moursy, Ali El-Moursy, Junmou Zhang, Wendi Beth Heinzelman:
1-V ADPCM Processor for Low-Power Wireless Applications.
386-393 BibTeX
- Ehsan Atoofian, Zainalabedin Navabi:
A Low Power BIST Architecture for FPGA Look-Up Table Testing.
394-397 BibTeX
- Adão Antônio de Souza Jr., Luigi Carro:
An All-Digital ADC for Instrumentation within SOCs.
398-403 BibTeX
- Diego Caldas Salengue, João Baptista dos Santos Martins, Cesar Ramos Rodrigues, André Luiz Aita:
FPGA Implementation of a VVI Temporary Pacemaker Digital Control.
404-409 BibTeX
- Fernando da Rocha Paixão Cortes, Eric E. Fabris, Sergio Bampi:
Applying the GM/ID method in the analysis and design of Miller Amplifier, Comparator and GM-C PASS-B.
410-415 BibTeX
- Hemanth Sampath, Ranga Vemuri:
MSL: A High-Level Language for Parameterized Analog and Mixed Signal Layout Generators.
416-421 BibTeX
- André Luiz Aita, João Baptista dos Santos Martins, César Augusto Prior, Cesar Ramos Rodrigues:
Low-Power High-CMRR CMOS Instrumentation Amplifier for Biomedical Applications.
422-425 BibTeX
- Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi:
A Genetic Approach To Bus Encoding.
426-431 BibTeX
- Arturo Méndez Patiño, Marcos Martínez Peiró:
2D-DCT Implementation on FPGA by Polynomial Transformation in Two-Dimensions.
432-438 BibTeX
- Jari Nikara, Stamatis Vassiliadis, Jarmo Takala, Petri Liuha:
FPGA-Based Variable Length Decoders.
437-441 BibTeX
- Stephan Bingemer, Peter Zipf, Manfred Glesner:
An Integrated Model Bridging the Gap between Technology and Economy.
442- BibTeX
Ph.D Forum
Copyright © Sat May 16 23:46:40 2009
by Michael Ley (ley@uni-trier.de)
