Volume 28,
Number 1,
January 2009
- Radu Marculescu, Ümit Y. Ogras, Li-Shiuan Peh, Natalie D. Enright Jerger, Yatin Vasant Hoskote:
Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives.
3-21
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- Paolo Maffezzoni, Dario D'Amore:
Evaluating Pulling Effects in Oscillators Due to Small-Signal Injection.
22-31
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- Ender Yilmaz, Günhan Dündar:
Analog Layout Generator for CMOS Circuits.
32-45
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- Jing Li, Kunhyuk Kang, Kaushik Roy:
Variation Estimation and Compensation Technique in Scaled LTPS TFT Circuits for Low-Power Low-Cost Applications.
46-59
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- María C. Molina, Rafael Ruiz-Sautua, Pedro Garcia-Repetto, Román Hermida:
Frequent-Pattern-Guided Multilevel Decomposition of Behavioral Specifications.
60-73
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- Smita Krishnaswamy, Stephen Plaza, Igor L. Markov, John P. Hayes:
Signature-Based SER Analysis and Design of Logic Circuits.
74-86
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- Jung Hwan Choi, Nilanjan Banerjee, Kaushik Roy:
Variation-Aware Low-Power Synthesis Methodology for Fixed-Point FIR Filters.
87-97
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- Jia-Wei Fang, Chin-Hsiung Hsu, Yao-Wen Chang:
An Integer-Linear-Programming-Based Routing Algorithm for Flip-Chip Designs.
98-110
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- Sudarshan Bahukudumbi, Krishnendu Chakrabarty:
Test-Length and TAM Optimization for Wafer-Level Reduced Pin-Count Testing of Core-Based SoCs.
111-120
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- Irith Pomeranz, Sudhakar M. Reddy:
Functional Broadside Tests Under an Expanded Definition of Functional Operation Conditions.
121-129
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- Lerong Cheng, Jinjun Xiong, Lei He:
Non-Gaussian Statistical Timing Analysis Using Second-Order Polynomial Fitting.
130-140
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- Zhuo Feng, Peng Li, Yaping Zhan:
An On-the-Fly Parameter Dimension Reduction Approach to Fast Second-Order Statistical Static Timing Analysis.
141-153
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- Gianpiero Cabodi, Sergio Nocco, Stefano Quer:
Strengthening Model Checking Techniques With Inductive Invariants.
154-158
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- Hoseok Chang, Wonyong Sung:
Access-Pattern-Aware On-Chip Memory Allocation for SIMD Processors.
158-163
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Volume 28,
Number 2,
February 2009
- Cheng-Hong Li, Luca P. Carloni:
Leveraging Local Intracore Information to Increase Global Performance in Block-Based Design of Systems-on-Chip.
165-178
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- Kristofer Vorwerk, Andrew A. Kennings, Jonathan W. Greene:
Improving Simulated Annealing-Based FPGA Placement With Directed Moves.
179-192
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- Huang-Yu Chen, Szu-Jui Chou, Sheng-Lung Wang, Yao-Wen Chang:
A Novel Wire-Density-Driven Full-Chip Routing System for CMP Variation Control.
193-206
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- Shenghua Liu, Guoqiang Chen, Tom Tong Jing, Lei He, Tianpei Zhang, Robi Dutta, Xian-Long Hong:
Substrate Topological Routing for High-Density Packages.
207-216
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- Huaizhi Wu, Martin D. F. Wong:
Incremental Improvement of Voltage Assignment.
217-230
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- Cristian Soviani, Ilija Hadzic, Stephen A. Edwards:
Synthesis and Optimization of Pipelined Packet Processors.
231-244
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- Vishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski:
Timing-Aware Multiple-Delay-Fault Diagnosis.
245-258
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- Zhanglei Wang, Hongxia Fang, Krishnendu Chakrabarty, Michael Bienek:
Deviation-Based LFSR Reseeding for Test-Data Compression.
259-271
Electronic Edition (link) BibTeX
- Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou:
Accurate Rank Ordering of Error Candidates for Efficient HDL Design Debugging.
272-284
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- Ho Fai Ko, Nicola Nicolici:
Algorithms for State Restoration and Trace-Signal Selection for Data Acquisition in Silicon Debug.
285-297
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- Sobeeh Almukhaizim, Ozgur Sinanoglu:
Dynamic Scan Chain Partitioning for Reducing Peak Shift Power During Test.
298-302
Electronic Edition (link) BibTeX
Volume 28,
Number 3,
March 2009
- Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung:
Combining Data Reuse With Data-Level Parallelization for FPGA-Targeted Hardware Compilation: A Geometric Programming Framework.
305-315
Electronic Edition (link) BibTeX
- Dipanjan Sengupta, Resve A. Saleh:
Application-Driven Voltage-Island Partitioning for Low-Power System-on-Chip Design.
316-326
Electronic Edition (link) BibTeX
- Youngsoo Shin, Seungwhun Paik, Hyung-Ock Kim:
Semicustom Design of Zigzag Power-Gated Circuits in Standard Cell Elements.
327-339
Electronic Edition (link) BibTeX
- Muhammet Mustafa Ozdal:
Detailed-Routing Algorithms for Dense Pin Clusters in Integrated Circuits.
340-349
Electronic Edition (link) BibTeX
- Hushrav Mogal, Haifeng Qian, Sachin S. Sapatnekar, Kia Bazargan:
Fast and Accurate Statistical Criticality Computation Under Process Variations.
350-363
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- Alessandro Pinto, Luca P. Carloni, Alberto L. Sangiovanni-Vincentelli:
A Methodology for Constraint-Driven Synthesis of On-Chip Communications.
364-377
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- Martino Ruggiero, Davide Bertozzi, Luca Benini, Michela Milano, A. Andrei:
Reducing the Abstraction and Optimality Gaps in the Allocation and Scheduling for Variable Voltage/Frequency MPSoC Platforms.
378-391
Electronic Edition (link) BibTeX
- Mihir R. Choudhury, Kartik Mohanram:
Reliability Analysis of Logic Circuits.
392-405
Electronic Edition (link) BibTeX
- S. Saqib Khursheed, Bashir M. Al-Hashimi, Sudhakar M. Reddy, Peter Harrod:
Diagnosis of Multiple-Voltage Design With Bridge Defect.
406-416
Electronic Edition (link) BibTeX
- Yu-Min Kuo, Yue-Lung Chang, Shih-Chieh Chang:
Efficient Boolean Characteristic Function for Timed Automatic Test Pattern Generation.
417-425
Electronic Edition (link) BibTeX
- Irith Pomeranz, Sudhakar M. Reddy:
Double-Single Stuck-at Faults: A Delay Fault Model for Synchronous Sequential Circuits.
426-432
Electronic Edition (link) BibTeX
- Haiqiong Yao, Hao Zheng:
Automated Interface Refinement for Compositional Verification.
433-446
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- Angelo Brambilla, Giambattista Gruosso, Giancarlo Storti Gajani:
Determination of Floquet Exponents for Small-Signal Analysis of Nonlinear Periodic Circuits.
447-451
Electronic Edition (link) BibTeX
- Eunjoo Choi, Changsik Shin, Youngsoo Shin:
ssr HLShbox-ssr pg: High-Level Synthesis of Power-Gated Circuits.
451-456
Electronic Edition (link) BibTeX
- Yu-Min Kuo, Ya-Ting Chang, Shih-Chieh Chang, Malgorzata Marek-Sadowska:
Spare Cells With Constant Insertion for Engineering Change.
456-460
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- Aviral Shrivastava, Ilya Issenin, Nikil Dutt, Sanghyun Park, Yunheung Paek:
Compiler-in-the-Loop Design Space Exploration Framework for Energy Reduction in Horizontally Partitioned Cache Architectures.
461-465
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Volume 28,
Number 4,
April 2009
- Pramod Kumar Meher:
Extended Sequential Logic for Synchronous Circuit Optimization and Its Applications.
469-477
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- Behnam Amelifard, Farzan Fallah, Massoud Pedram:
Low-Power Fanout Optimization Using Multi Threshold Voltages and Multi Channel Lengths.
478-489
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- Wei Dong, Peng Li:
A Parallel Harmonic-Balance Approach to Steady-State and Envelope-Following Simulation of Driven and Autonomous Circuits.
490-501
Electronic Edition (link) BibTeX
- Yongfeng Feng, H. Alan Mantooth:
Algorithms for Automatic Model Topology Formulation.
502-515
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- Vittorio Rizzoli, Franco Mastri, Alessandra Costanzo, Diego Masotti:
Harmonic-Balance Algorithms for the Circuit-Level Nonlinear Analysis of UWB Receivers in the Presence of Interfering Signals.
516-527
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- Muhammet Mustafa Ozdal, Martin D. F. Wong:
Archer: A History-Based Global Routing Algorithm.
528-540
Electronic Edition (link) BibTeX
- Takashi Enami, Shinyu Ninomiya, Masanori Hashimoto:
Statistical Timing Analysis Considering Spatially and Temporally Correlated Dynamic Power Supply Noise.
541-553
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- Doosan Cho, Sudeep Pasricha, Ilya Issenin, Nikil D. Dutt, Minwook Ahn, Yunheung Paek:
Adaptive Scratch Pad Memory Management for Dynamic Behavior of Multimedia Applications.
554-567
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- Jungsoo Kim, Seungyong Oh, Sungjoo Yoo, Chong-Min Kyung:
An Analytical Dynamic Scaling of Supply Voltage and Body Bias Based on Parallelism-Aware Workload and Runtime Distribution.
568-581
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- Haralampos-G. D. Stratigopoulos, Salvador Mir, Ahcène Bounceur:
Evaluation of Analog/RF Test Measurements at the Design Stage.
582-590
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- Yu Hu, Satyaki Das, Steven Trimberger, Lei He:
Design and Synthesis of Programmable Logic Block With Mixed LUT and Macrogate.
591-595
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- Alodeep Sanyal, Kunal P. Ganeshpure, Sandip Kundu:
An Improved Soft-Error Rate Measurement Technique.
596-600
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- Shuo Wang, Lei Wang:
Analysis of Deskew Signaling Via Adaptive Timing.
601-605
Electronic Edition (link) BibTeX
Copyright © Sun May 17 00:23:19 2009
by Michael Ley (ley@uni-trier.de)