| 1999 |
|---|
| 15 | EE | Uwe Sparmann,
H. Mueller,
Sudhakar M. Reddy:
Universal delay test sets for logic networks.
IEEE Trans. VLSI Syst. 7(2): 156-166 (1999) |
| 1998 |
|---|
| 14 | EE | Uwe Sparmann,
Lars Köller:
Improving Path Delay Fault Testability by Path Removal.
VTS 1998: 200-209 |
| 1996 |
|---|
| 13 | EE | Uwe Sparmann,
H. Mueller,
Sudhakar M. Reddy:
Minimal Delay Test Sets for Unate Gate Networks.
Asian Test Symposium 1996: 155- |
| 12 | | Harry Hengster,
Uwe Sparmann,
Bernd Becker,
Sudhakar M. Reddy:
Local Transformations and Robust Dependent Path Delay.
ITC 1996: 347-356 |
| 11 | EE | Prasanti Uppaluri,
Uwe Sparmann,
Irith Pomeranz:
On minimizing the number of test points needed to achieve complete robust path delay fault testability.
VTS 1996: 288-295 |
| 10 | EE | Uwe Sparmann,
Sudhakar M. Reddy:
On the effectiveness of residue code checking for parallel two's complement multipliers.
IEEE Trans. VLSI Syst. 4(2): 227-239 (1996) |
| 1995 |
|---|
| 9 | EE | Uwe Sparmann,
D. Luxenburger,
Kwang-Ting Cheng,
Sudhakar M. Reddy:
Fast Identification of Robust Dependent Path Delay Faults.
DAC 1995: 119-125 |
| 1994 |
|---|
| 8 | | Uwe Sparmann,
Sudhakar M. Reddy:
On the Effectiveness of Residue Code Checking for Parallel Two's Complement Multipliers.
FTCS 1994: 219-228 |
| 7 | | Thomas Burch,
J. Hartmann,
Günter Hotz,
M. Krallmann,
U. Nikolaus,
Sudhakar M. Reddy,
Uwe Sparmann:
A Hierarchical Environment for Interactive Test Engineering.
ITC 1994: 461-470 |
| 6 | | Paul Molitor,
Uwe Sparmann,
Dorothea Wagner:
Two-Layer Wiring with Pin Preassignments is Easier if the Power Supply Nets are Already Generated.
VLSI Design 1994: 149-154 |
| 1991 |
|---|
| 5 | | Bernd Becker,
Uwe Sparmann:
A uniform test approach for RCC-adders.
Fundam. Inform. 14(2): 185-219 (1991) |
| 4 | | Bernd Becker,
Uwe Sparmann:
Computations over Finite Monoids and their Test Complexity.
Theor. Comput. Sci. 84(2): 225-250 (1991) |
| 1990 |
|---|
| 3 | EE | Bernd Becker,
Thomas Burch,
Günter Hotz,
D. Kiel,
Reiner Kolla,
Paul Molitor,
Hans-Georg Osthof,
Gisela Pitsch,
Uwe Sparmann:
A graphical system for hierarchical specifications and checkups of VLSI circuits.
EURO-DAC 1990: 174-179 |
| 1988 |
|---|
| 2 | | Bernd Becker,
Uwe Sparmann:
Regular Structures and Testing: RCC-Adders.
AWOC 1988: 288-300 |
| 1 | | Uwe Sparmann:
Design and Test of a Pattern Matching Circuit.
Elektronische Informationsverarbeitung und Kybernetik 24(7/8): 329-338 (1988) |
