| |
| 1996 | ||
|---|---|---|
| 4 | EE | Prasanti Uppaluri, Uwe Sparmann, Irith Pomeranz: On minimizing the number of test points needed to achieve complete robust path delay fault testability. VTS 1996: 288-295 |
| 1995 | ||
| 3 | EE | Irith Pomeranz, Sudhakar M. Reddy, Prasanti Uppaluri: NEST: a nonenumerative test generation method for path delay faults in combinational circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 14(12): 1505-1515 (1995) |
| 1994 | ||
| 2 | Prasanti Uppaluri, Irith Pomeranz, Sudhakar M. Reddy: Test Pattern Generation for Path Delay Faults in Synchronous Sequential Circuits Using Multiple Fast Clocks and Multiple Observations Times. FTCS 1994: 456-465 | |
| 1993 | ||
| 1 | EE | Irith Pomeranz, Sudhakar M. Reddy, Prasanti Uppaluri: NEST: A Non-Enumerative Test Generation Method for Path Delay Faults in Combinational Circuits. DAC 1993: 439-445 |
| 1 | Irith Pomeranz | [1] [2] [3] [4] |
| 2 | Sudhakar M. Reddy | [1] [2] [3] |
| 3 | Uwe Sparmann | [4] |