Vamsi Boppana

2008
31	EE	Shashank Bhonge, Vamsi Boppana: Low power chips: a fabless asic perspective. ISLPED 2008: 347-348
30	EE	Vamsi Boppana, Rahoul Varma, S. Balajee: Implementing the Best Processor Cores. VLSI Design 2008: 17-18
2005
29	EE	Rob Roy, Debashis Bhattacharya, Vamsi Boppana: Transistor-Level Optimization of Digital Designs with Flex Cells. IEEE Computer 38(2): 53-61 (2005)
2004
28	EE	Hiroaki Yoshida, Kaushik De, Vamsi Boppana: Accurate pre-layout estimation of standard cell characteristics. DAC 2004: 208-211
2003
27	EE	Enamul Amyeen, W. Kent Fuchs, Irith Pomeranz, Vamsi Boppana: Fault equivalence identification in combinational circuits using implication and evaluation techniques. IEEE Trans. on CAD of Integrated Circuits and Systems 22(7): 922-936 (2003)
2002
26	EE	Indradeep Ghosh, Krishna Sekar, Vamsi Boppana: Design for Verification at the Register Transfer Level. VLSI Design 2002: 420-425
2001
25	EE	Biplab K. Sikdar, Debesh K. Das, Vamsi Boppana, Cliff Yang, Sobhan Mukherjee, Parimal Pal Chaudhuri: Cellular automata as a built in self test structure. ASP-DAC 2001: 319-324
24	EE	Enamul Amyeen, W. Kent Fuchs, Irith Pomeranz, Vamsi Boppana: Fault Equivalence Identification Using Redundancy Information and Static and Dynamic Extraction. VTS 2001: 124-130
23	EE	Srivaths Ravi, Indradeep Ghosh, Vamsi Boppana, Niraj K. Jha: Fault-diagnosis-based technique for establishing RTL and gate-levelcorrespondences. IEEE Trans. on CAD of Integrated Circuits and Systems 20(12): 1414-1425 (2001)
2000
22	EE	Srivaths Ravi, Niraj K. Jha, Indradeep Ghosh, Vamsi Boppana: A Technique for Identifying RTL and Gate-Level Correspondences. ICCD 2000: 591-
21	EE	Vamsi Boppana, Indradeep Ghosh, Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita: Hierarchical Error Diagnosis Targeting RTL Circuits. VLSI Design 2000: 436-441
20	EE	Biplab K. Sikdar, Kolin Paul, Gosta Pada Biswas, Parimal Pal Chaudhuri, Vamsi Boppana, Cliff Yang, Sobhan Mukherjee: Theory and Application of GF(2p) Cellular Automata as On-chip Test Pattern Generator. VLSI Design 2000: 556-561
19	EE	Ankur Jain, Vamsi Boppana, Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita, Michael S. Hsiao: Testing, Verification, and Diagnosis in the Presence of Unknowns. VTS 2000: 263-270
1999
18	EE	Vamsi Boppana, Sreeranga P. Rajan, Koichiro Takayama, Masahiro Fujita: Model Checking Based on Sequential ATPG. CAV 1999: 418-430
17	EE	Vamsi Boppana, Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita, Pradeep Bollineni: Multiple Error Diagnosis Based on Xlists. DAC 1999: 660-665
16	EE	Enamul Amyeen, W. Kent Fuchs, Irith Pomeranz, Vamsi Boppana: Implication and Evaluation Techniques for Proving Fault Equivalence. VTS 1999: 201-213
15	EE	Ankur Jain, Michael S. Hsiao, Vamsi Boppana, Masahiro Fujita: On the Evaluation of Arbitrary Defect Coverage of Test Sets. VTS 1999: 426-432
1998
14	EE	Vamsi Boppana, W. Kent Fuchs: Dynamic fault collapsing and diagnostic test pattern generation for sequential circuits. ICCAD 1998: 147-154
13	EE	Vamsi Boppana, Masahiro Fujita: Modeling the unknown! Towards model-independent fault and error diagnosis. ITC 1998: 1094-
1997
12	EE	Vamsi Boppana, Ismed Hartanto, W. Kent Fuchs: Characterization and Implicit Identification of Sequential Indistinguishability. VLSI Design 1997: 376-380
11	EE	Ismed Hartanto, Vamsi Boppana, Janak H. Patel, W. Kent Fuchs: Diagnostic Test Pattern Generation for Sequential Circuits. VTS 1997: 196-202
1996
10		Vamsi Boppana, Prashant Saxena, Prithviraj Banerjee, W. Kent Fuchs, C. L. Liu: A Parallel Algorithm for the Technology Mapping of LUT-Based FPGAs. Euro-Par, Vol. I 1996: 828-831
9		Vamsi Boppana, Ismed Hartanto, W. Kent Fuchs: Fault Diagnosis Using State Information. FTCS 1996: 96-103
8	EE	Ismed Hartanto, Vamsi Boppana, W. Kent Fuchs: Identification of unsettable flip-flops for partial scan and faster ATPG. ICCAD 1996: 63-66
7	EE	Vamsi Boppana, W. Kent Fuchs: Integrated fault diagnosis targeting reduced simulation. ICCAD 1996: 681-684
6		Ismed Hartanto, Vamsi Boppana, W. Kent Fuchs: Diagnostic Fault Equivalence Identification Using Redundancy Information and Structural Analysis. ITC 1996: 294-302
5		Vamsi Boppana, W. Kent Fuchs: Partial Scan Design Based on State Transition Modeling. ITC 1996: 538-547
4	EE	Vamsi Boppana, Ismed Hartanto, W. Kent Fuchs: Full fault dictionary storage based on labeled tree encoding. VTS 1996: 174-179
1994
3	EE	Vamsi Boppana, W. Kent Fuchs: Fault dictionary compaction by output sequence removal. ICCAD 1994: 576-579
2		S. Nandi, Vamsi Boppana, Parimal Pal Chaudhuri: A CAD Tool for Design of On-Chip Store & Generate Scheme. VLSI Design 1994: 169-174
1993
1		S. Nandi, Vamsi Boppana, Supratik Chakraborty, Parimal Pal Chaudhuri, Samir Roy: Delay Fault Test Generation with Cellular Automata. VLSI Design 1993: 281-286

Coauthor Index

1	Enamul Amyeen	[16] [24] [27]
2	S. Balajee	[30]
3	Prithviraj Banerjee (Prith Banerjee)	[10]
4	Debashis Bhattacharya	[29]
5	Shashank Bhonge	[31]
6	Gosta Pada Biswas	[20]
7	Pradeep Bollineni	[17]
8	Supratik Chakraborty	[1]
9	Parimal Pal Chaudhuri	[1] [2] [20] [25]
10	Debesh Kumar Das (Debesh K. Das)	[25]
11	Kaushik De	[28]
12	W. Kent Fuchs	[3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [14] [16] [24] [27]
13	Masahiro Fujita	[13] [15] [17] [18] [19] [21]
14	Indradeep Ghosh	[21] [22] [23] [26]
15	Ismed Hartanto	[4] [6] [8] [9] [11] [12]
16	Michael S. Hsiao	[15] [19]
17	Ankur Jain	[15] [19]
18	Jawahar Jain	[17] [19] [21]
19	Niraj K. Jha	[22] [23]
20	C. L. Liu (Chung Laung (Dave) Liu)	[10]
21	Rajarshi Mukherjee	[17] [19] [21]
22	Sobhan Mukherjee	[20] [25]
23	S. Nandi	[1] [2]
24	Janak H. Patel	[11]
25	Kolin Paul	[20]
26	Irith Pomeranz	[16] [24] [27]
27	Sreeranga P. Rajan	[18]
28	Srivaths Ravi	[22] [23]
29	Rob Roy	[29]
30	Samir Roy	[1]
31	Prashant Saxena	[10]
32	Krishna Sekar	[26]
33	Biplab K. Sikdar	[20] [25]
34	Koichiro Takayama	[18]
35	Rahoul Varma	[30]
36	Cliff Yang	[20] [25]
37	Hiroaki Yoshida	[28]

Colors in the list of coauthors