6th Great Lakes Symposium on VLSI (GLS-VLSI '96), March 22-23, 1996, Ames, IA, USA.
IEEE Computer Society 1996 BibTeX
@proceedings{DBLP:conf/glvlsi/1996,
title = {6th Great Lakes Symposium on VLSI (GLS-VLSI '96), March 22-23,
1996, Ames, IA, USA},
booktitle = {Great Lakes Symposium on VLSI},
publisher = {IEEE Computer Society},
year = {1996},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
High-level Synthesis and Special Purpose Architecture I
Circuit Design and FPGA Architecture II
Physical Design I
High-level Synthesis and Special Purpose Architecture II
Physical Design II
Synthesis and Verification I
Special Session on Issues in Performance Driven Layout
Low Power Design
Physical Design III
Testing I
High-level Synthesis and Special Purpose Architecture III
Circuit Design II
- José G. Delgado-Frias, Jabulani Nyathi, Chester L. Miller, Douglas H. Summerville:
A VLSI Interconnection Network Router Using a D-CAM with Hidden Refresh.
246-251
Electronic Edition (link) BibTeX
- L. Desormeaux, V. Szwarc, J. Lodge:
A High-Speed, Real-to-Quadrature Converter with Filtering and Decimation.
252-255
Electronic Edition (link) BibTeX
- Maher E. Rizkalla, Richard L. Aldridge, Nadeem A. Khan, Harry C. Gundrum:
A CMOS VLSI Implementation of an NxN Multiplexing Circuitry for ATM Applications.
256-259
Electronic Edition (link) BibTeX
- Jai-Sop Hyun, Kwang Sub Yoon:
A 3V-50MHz Analog CMOS Current-Mode High Frequency Filter with a Negative Resistance Load.
260-
Electronic Edition (link) BibTeX
Synthesis and Verification II
Testing II
Copyright © Sat May 16 23:13:52 2009
by Michael Ley (ley@uni-trier.de)
