Volume 16,
Numbers 1-2,
February 2000
- Vishwani D. Agrawal:
Editorial.
5
Electronic Edition (link) BibTeX
- Magdy S. Abadir:
Guest Editorial.
9-10
Electronic Edition (link) BibTeX
- Ta-Chung Chang, Vikram Iyengar, Elizabeth M. Rudnick:
A Biased Random Instruction Generation Environment for Architectural Verification of Pipelined Processors.
13-27
Electronic Edition (link) BibTeX
- Pradip Bose:
Testing for Function and Performance: Towards an Integrated Processor Validation Methodology.
29-48
Electronic Edition (link) BibTeX
- Noppanunt Utamaphethai, R. D. (Shawn) Blanton, John Paul Shen:
A Buffer-Oriented Methodology for Microarchitecture Validation.
49-65
Electronic Edition (link) BibTeX
- Jian Shen, Jacob A. Abraham:
An RTL Abstraction Technique for Processor Microarchitecture Validation and Test Generation.
67-81
Electronic Edition (link) BibTeX
- Byeong Min, Gwan Choi:
Verification Simulation Acceleration Using Code-Perturbation.
83-90
Electronic Edition (link) BibTeX
- Jaehong Park, Carl Pixley, Michael Burns, Hyunwoo Cho:
An Efficient Logic Equivalence Checker for Industrial Circuits.
91-106
Electronic Edition (link) BibTeX
- Jun Yuan, Kurt Shultz, Carl Pixley, Hillel Miller, Adnan Aziz:
Automatic Vector Generation Using Constraints and Biasing.
107-120
Electronic Edition (link) BibTeX
- Li-C. Wang, Magdy S. Abadir:
On Efficiently Producing Quality Tests for Custom Circuits in PowerPCTM Microprocessors.
121-130
Electronic Edition (link) BibTeX
- Sandhya Seshadri, Michael S. Hsiao:
Formal Value-Range and Variable Testability Techniques for High-Level Design-For-Testability.
131-145
Electronic Edition (link) BibTeX
- Wen Ching Wu, Chung-Len Lee, Ming Shae Wu, Jwu E. Chen, Magdy S. Abadir:
Oscillation Ring Delay Test for High Performance Microprocessors.
147-155
Electronic Edition (link) BibTeX
Volume 16,
Number 3,
June 2000
- Vishwani D. Agrawal:
Editorial.
163
Electronic Edition (link) BibTeX
- Christian Landrault:
Guest Editorial.
167
Electronic Edition (link) BibTeX
- Gundolf Kiefer, Hans-Joachim Wunderlich:
Deterministic BIST with Partial Scan.
169-177
Electronic Edition (link) BibTeX
- Alfredo Benso, Silvia Cataldo, Silvia Chiusano, Paolo Prinetto, Yervant Zorian:
A High-Level EDA Environment for the Automatic Insertion of HD-BIST Structures.
179-184
Electronic Edition (link) BibTeX
- A. Schubert, Walter Anheier:
On Random Pattern Testability of Cryptographic VLSI Cores.
185-192
Electronic Edition (link) BibTeX
- Salvador Manich, A. Gabarró, M. Lopez, Joan Figueras, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, P. Teixeira, M. Santos:
Low Power BIST by Filtering Non-Detecting Vectors.
193-202
Electronic Edition (link) BibTeX
- Stefan Gerstendörfer, Hans-Joachim Wunderlich:
Minimized Power Consumption for Scan-Based BIST.
203-212
Electronic Edition (link) BibTeX
- Jaan Raik, Raimund Ubar:
Fast Test Pattern Generation for Sequential Circuits Using Decision Diagram Representations.
213-226
Electronic Edition (link) BibTeX
- Hans A. R. Manhaeve, Johan Verfaillie, B. Straka, J. P. Cornil:
Application of Supply Current Testing to Analogue Circuits, Towards a Structural Analogue Test Methodology.
227-234
Electronic Edition (link) BibTeX
- Rodrigo Picos, Miquel Roca, Eugeni Isern, Jaume Segura, Eugeni García-Moreno:
Experimental Results on BIC Sensors for Transient Current Testing.
235-241
Electronic Edition (link) BibTeX
- Toshiyuki Maeda, Kozo Kinoshita:
Compaction of IDDQ Test Sequence Using Reassignment Method.
243-249
Electronic Edition (link) BibTeX
- Anna Maria Brosa, Joan Figueras:
On Maximizing the Coverage of Catastrophic and Parametric Faults.
251-258
Electronic Edition (link) BibTeX
- Michel Renovell, Florence Azaïs, J-C. Bodin, Yves Bertrand:
Combining Functional and Structural Approaches for Switched-Current Circuit Testing.
259-267
Electronic Edition (link) BibTeX
- Abdelhakim Khouas, Anne Derieux:
Fault Simulation for Analog Circuits Under Parameter Variations.
269-278
Electronic Edition (link) BibTeX
- Salvador Mir, Benoît Charlot, Bernard Courtois:
Extending Fault-Based Testing to Microelectromechanical Systems.
279-288
Electronic Edition (link) BibTeX
- Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian:
An Approach to Minimize the Test Configuration for the Logic Cells of the Xilinx XC4000 FPGAs Family.
289-299
Electronic Edition (link) BibTeX
- Harald P. E. Vranken:
Debug Facilities in the TriMedia CPU64 Architecture.
301-308
Electronic Edition (link) BibTeX
Volume 16,
Number 4,
August 2000
Volume 16,
Number 5,
October 2000
- Vishwani D. Agrawal:
Editorial.
403-404
Electronic Edition (link) BibTeX
- Serge N. Demidenko:
Guest Editorial.
407-408
Electronic Edition (link) BibTeX
- Bechir Ayari, Prab Varma:
Test Cycle Count Reduction in a Parallel Scan BIST Environment.
409-418
Electronic Edition (link) BibTeX
- Xiaowei Li, Paul Y. S. Cheung, Hideo Fujiwara:
LFSR-Based Deterministic TPG for Two-Pattern Testing.
419-426
Electronic Edition (link) BibTeX
- Chen-Huan Chiang, Sandeep K. Gupta:
BIST TPG for Combinational Cluster Interconnect Testing at Board Level.
427-442
Electronic Edition (link) BibTeX
- Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita:
Algorithms to Select IDDQ Measurement Vectors for Bridging Faults in Sequential Circuits.
443-451
Electronic Edition (link) BibTeX
- Márta Rencz, Vladimir Székely, S. Török, Kholdoun Torki, Bernard Courtois:
IDDQ Testing of Submicron CMOS - by Cooling?
453-461
Electronic Edition (link) BibTeX
- Marwan A. Gharaybeh, Vishwani D. Agrawal, Michael L. Bushnell, Carlos G. Parodi:
False-Path Removal Using Delay Fault Simulation.
463-476
Electronic Edition (link) BibTeX
- Huawei Li, Zhongcheng Li, Yinghua Min:
Reduction of Number of Paths to be Tested in Delay Testing.
477-485
Electronic Edition (link) BibTeX
- Said Hamdioui, A. J. van de Goor:
Testing Address Decoder Faults in Two-Port Memories: Fault Models, Tests, Consequences of Port Restrictions, and Test Strategy.
487-498
Electronic Edition (link) BibTeX
- Jian Liu, Rafic Z. Makki, Ayman I. Kayssi:
Dynamic Power Supply Current Testing of CMOS SRAMs.
499-511
Electronic Edition (link) BibTeX
- Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian:
Testing the Local Interconnect Resources of SRAM-Based FPGA's.
513-520
Electronic Edition (link) BibTeX
- Surendra Bommu, Kiran B. Doreswamy, Srimat T. Chakradhar:
A Practical Vector Restoration Technique for Large Sequential Circuits.
521-539
Electronic Edition (link) BibTeX
- Irith Pomeranz, Sudhakar M. Reddy:
Static Test Compaction for Scan-Based Designs to Reduce Test Application Time.
541-552
Electronic Edition (link) BibTeX
- Satoshi Ohtake, Toshimitsu Masuzawa, Hideo Fujiwara:
A Non-Scan Approach to DFT for Controllers Achieving 100% Fault Efficiency.
553-566
Electronic Edition (link) BibTeX
Volume 16,
Number 6,
December 2000
Copyright © Sat May 16 23:58:52 2009
by Michael Ley (ley@uni-trier.de)
