Volume 19,
Number 1,
February 2003
- Vishwani D. Agrawal:
Editorial.
5
Electronic Edition (link) BibTeX
- André Ivanov:
Test Technology Technical Council Newsletter.
7-8
Electronic Edition (link) BibTeX
- Víctor H. Champac, Ingrid Jansch-Pôrto:
Guest Editorial.
11
Electronic Edition (link) BibTeX
- L. Cassol, O. Betat, Luigi Carro, Marcelo Lubaszewski:
The SigmaDelta-BIST Method Applied to Analog Filters.
13-20
Electronic Edition (link) BibTeX
- Gladys Omayra Ducoudray, Jaime Ramírez-Angulo:
Innovative Built-In Self-Test Schemes for On-Chip Diagnosis, Compliant with the IEEE 1149.4 Mixed-Signal Test Bus Standard.
21-28
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- Luis Hernández-Martínez, Arturo Sarmiento-Reyes:
Topological Considerations for the Diagnosability Conditions of Analogue Circuits Using a Pair of Conjugate Trees.
29-36
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- Ilia Polian, Bernd Becker:
Multiple Scan Chain Design for Two-Pattern Testing.
37-48
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- Marie-Lise Flottes, Christian Landrault, A. Petitqueux:
A Unified DFT Approach for BIST and External Test.
49-60
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- Fabian Vargas, Rubem Dutra Ribeiro Fagundes, Daniel Barros Jr.:
A New On-Line Robust Approach to Design Noise-Immune Speech Recognition Systems.
61-72
Electronic Edition (link) BibTeX
- Raimund Ubar:
Design Error Diagnosis with Re-Synthesis in Combinational Circuits.
73-82
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- Raoul Velazco, Sana Rezgui, Haissam Ziade:
Assessing the Soft Error Rate of Digital Architectures Devoted to Operate in Radiation Environment: A Case Studied.
83-90
Electronic Edition (link) BibTeX
Volume 19,
Number 2,
April 2003
- Vishwani D. Agrawal:
Editorial.
95
Electronic Edition (link) BibTeX
- André Ivanov:
Test Technology Technical Council Newsletter.
99-100
Electronic Edition (link) BibTeX
- André Ivanov:
Guest Editorial.
101-102
Electronic Edition (link) BibTeX
- Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos, Yervant Zorian:
Instruction-Based Self-Testing of Processor Cores.
103-112
Electronic Edition (link) BibTeX
- Krishna Sekar, Sujit Dey:
LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects.
113-123
Electronic Edition (link) BibTeX
- Erik H. Volkerink, Ajay Khoche, Jochen Rivoir, Klaus D. Hilliges:
Modern Test Techniques: Tradeoffs, Synergies, and Scalable Benefits.
125-135
Electronic Edition (link) BibTeX
- Wanli Jiang, Eric Peterson:
Performance Comparison of VLV, ULV, and ECR Tests.
137-147
Electronic Edition (link) BibTeX
- Vivekananda M. Vedula, Jacob A. Abraham, Jayanta Bhadra, Raghuram S. Tupuri:
A Hierarchical Test Generation Approach Using Program Slicing Techniques on Hardware Description Languages.
149-160
Electronic Edition (link) BibTeX
- Shi-Yu Huang:
A Symbolic Inject-and-Evaluate Paradigm for Byzantine Fault Diagnosis.
161-172
Electronic Edition (link) BibTeX
- Sule Ozev, Alex Orailoglu:
Statistical Tolerance Analysis for Assured Analog Test Coverage.
173-182
Electronic Edition (link) BibTeX
- Takahiro J. Yamaguchi, Masahiro Ishida, Mani Soma, Louis Malarsie, Hirobumi Musha:
Timing Jitter Measurement of Intrinsic Random Jitter and Sinusoidal Jitter Using Frequency Division.
183-193
Electronic Edition (link) BibTeX
- Said Hamdioui, Zaid Al-Ars, A. J. van de Goor, Mike Rodgers:
Dynamic Faults in Random-Access-Memories: Concept, Fault Models and Tests.
195-205
Electronic Edition (link) BibTeX
- Jin-Fu Li, Ruey-Shing Tzeng, Cheng-Wen Wu:
Testing and Diagnosis Methodologies for Embedded Content Addressable Memories.
207-215
Electronic Edition (link) BibTeX
Volume 19,
Number 3,
June 2003
- Vishwani D. Agrawal:
Editorial.
219
Electronic Edition (link) BibTeX
- André Ivanov:
Test Technology Technical Council Newsletter.
221-222
Electronic Edition (link) BibTeX
- Christophe Fagot, Olivier Gascuel, Patrick Girard, Christian Landrault:
A Ring Architecture Strategy for BIST Test Pattern Generation.
223-231
Electronic Edition (link) BibTeX
- Dimitri Kagaris, Spyros Tragoudas:
LFSR Characteristic Polynomials for Pseudo-Exhaustive TPG with Low Number of Seeds.
233-244
Electronic Edition (link) BibTeX
- Hao-Yung Lo, Hsiu-Feng Lin, Chichyang Chen, Jenshiuh Liu, Chia-Cheng Liu:
Built-in Test with Modified-Booth High-Speed Pipelined Multipliers and Dividers.
245-269
Electronic Edition (link) BibTeX
- Hailong Cui, Sharad C. Seth, Shashank K. Mehta:
Modeling Fault Coverage of Random Test Patterns.
271-284
Electronic Edition (link) BibTeX
- Dimitris Gizopoulos, Mihalis Psarakis, Antonis M. Paschalis, Yervant Zorian:
Easily Testable Cellular Carry Lookahead Adders.
285-298
Electronic Edition (link) BibTeX
- Muhammad Nummer, Manoj Sachdev:
A DFT Technique for Testing High-Speed Circuits with Arbitrarily Slow Testers.
299-314
Electronic Edition (link) BibTeX
- Shyue-Kung Lu:
A Novel Built-In Self-Repair Approach for Embedded RAMs.
315-324
Electronic Edition (link) BibTeX
- Claude Thibeault:
Replacing IDDQ Testing: With Variance Reduction.
325-340
Electronic Edition (link) BibTeX
- Oleg Semenov, Arman Vassighi, Manoj Sachdev:
Leakage Current in Sub-Quarter Micron MOSFET: A Perspective on Stressed Delta IDDQ Testing.
341-352
Electronic Edition (link) BibTeX
- Josep Altet, André Ivanov, A. Wong:
Thermal Testing of Analogue Integrated Circuits: A Case Study.
353-357
Electronic Edition (link) BibTeX
Volume 19,
Number 4,
August 2003
Special Issue on the Seventh IEEE European Test Workshop
- Vishwani D. Agrawal:
Editorial.
363
Electronic Edition (link) BibTeX
- André Ivanov:
Test Technology Technical Council Newsletter.
365-366
Electronic Edition (link) BibTeX
- Christian Landrault:
Guest Editorial.
367
Electronic Edition (link) BibTeX
- Camelia Hora, Rene Segers, Stefan Eichenberger, Maurice Lousberg:
On a Statistical Fault Diagnosis Approach Enabling Fast Yield Ramp-Up.
369-376
Electronic Edition (link) BibTeX
- Michel Renovell, Jean Marc Gallière, Florence Azaïs, Yves Bertrand:
Modeling the Random Parameters Effects in a Non-Split Model of Gate Oxide Short.
377-386
Electronic Edition (link) BibTeX
- Jonathan Bradford, Hartmut Delong, Ilia Polian, Bernd Becker:
Simulating Realistic Bridging and Crosstalk Faults in an Industrial Setting.
387-395
Electronic Edition (link) BibTeX
- Frank te Beest, Ad M. G. Peeters, Kees van Berkel, Hans G. Kerkhoff:
Synchronous Full-Scan for Asynchronous Handshake Circuits.
397-406
Electronic Edition (link) BibTeX
- Sandeep Kumar Goel, Bart Vermeulen:
Data Invalidation Analysis for Scan-Based Debug on Multiple-Clock System Chips.
407-416
Electronic Edition (link) BibTeX
- Bart Vermeulen, Tom Waayers, Sjaak Bakker:
Multi-TAP Controller Architecture for Digital System Chips.
417-424
Electronic Edition (link) BibTeX
- Sandeep Kumar Goel, Erik Jan Marinissen:
A Test Time Reduction Algorithm for Test Architecture Design for Core-Based System Chips.
425-435
Electronic Edition (link) BibTeX
Special Issue on the Seventh IEEE European Test Workshop
- Xiao Liu, Michael S. Hsiao, Sreejit Chakravarty, Paul J. Thadikaran:
Efficient Transition Fault ATPG Algorithms Based on Stuck-At Test Vectors.
437-445
Electronic Edition (link) BibTeX
- Yun Shao, Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara:
On Selecting Testable Paths in Scan Designs.
447-456
Electronic Edition (link) BibTeX
- Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailoglu:
Reducing Average and Peak Test Power Through Scan Chain Modification.
457-467
Electronic Edition (link) BibTeX
- Serge Bernard, Florence Azaïs, Yves Bertrand, Michel Renovell:
On-Chip Generation of Ramp and Triangle-Wave Stimuli for ADC BIST.
469-479
Electronic Edition (link) BibTeX
- Martin John Burbidge, Frederic Poullet, Jim Tijou, Andrew Richardson:
Investigations for Minimum Invasion Digital Only Built-In "Ramp" Based Test Techniques for Charge Pump PLL's.
481-490
Electronic Edition (link) BibTeX
Volume 19,
Number 5,
October 2003
Special Issue on the Eighth IEEE International On-Line Testing Workshop (IOLTW'02)
- V. D. Agrawal:
Editorial.
495
Electronic Edition (link) BibTeX
- André Ivanov:
Test Technology Technical Council Newsletter.
497-498
Electronic Edition (link) BibTeX
- Cecilia Metra, Matteo Sonza Reorda:
Guest Editorial.
499
Electronic Edition (link) BibTeX
- Matthias Pflanz, K. Walther, Christian Galke, Heinrich Theodor Vierhaus:
On-Line Techniques for Error Detection and Correction in Processor Registers with Cross-Parity Check.
501-510
Electronic Edition (link) BibTeX
- Daniele Rossi, Cecilia Metra:
Error Correcting Strategy for High Speed and High Density Reliable Flash Memories.
511-521
Electronic Edition (link) BibTeX
- Parag K. Lala, B. Kiran Kumar:
An Architecture for Self-Healing Digital Systems.
523-535
Electronic Edition (link) BibTeX
- Feng Gao, John P. Hayes:
On-Line Monitor Design of Finite-State Machines.
537-548
Electronic Edition (link) BibTeX
- Miron Abramovici, Charles E. Stroud:
BIST-Based Delay-Fault Testing in FPGAs.
549-558
Electronic Edition (link) BibTeX
- Régis Leveugle, K. Hadjiat:
Multi-Level Fault Injections in VHDL Descriptions: Alternative Approaches and Experiments.
559-575
Electronic Edition (link) BibTeX
- Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante:
Accurate Analysis of Single Event Upsets in a Pipelined Microprocessor.
577-584
Electronic Edition (link) BibTeX
- Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin:
A Statistical Sampler for a New On-Line Analog Test Method.
585-595
Electronic Edition (link) BibTeX
- Joan Font, J. Ginard, Rodrigo Picos, Eugeni Isern, Jaume Segura, Miquel Roca, Eugenio García:
A BICS for CMOS OpAmps by Monitoring the Supply Current Peak.
597-603
Electronic Edition (link) BibTeX
Volume 19,
Number 6,
December 2003
Copyright © Sat May 16 23:58:52 2009
by Michael Ley (ley@uni-trier.de)
