ICCAD 2000:
San Jose,
California,
USA
Ellen Sentovich (Ed.):
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000, San Jose, California, USA, November 5-9, 2000.
IEEE 2000, ISBN 0-7803-6448-1 BibTeX
Floorplanning and Partitioning
High Level Simulation
Methods for DSP Synthesis and Debugging
Issues in Timing Estimation
- Yu Cao, Chenming Hu, Xuejue Huang, Andrew B. Kahng, Sudhakar Muddu, Dirk Stroobandt, Dennis Sylvester:
Effects of Global Interconnect Optimizations on Performance Estimation of Deep Submicron Design.
56-61 BibTeX
- Michael Orshansky, Linda Milor, Pinhong Chen, Kurt Keutzer, Chenming Hu:
Impact of Systematic Spatial Intra-Chip Gate Length Variability on Performance of High-Speed Digital Circuits.
62-67 BibTeX
- Pinhong Chen, Desmond Kirkpatrick, Kurt Keutzer:
Miller Factor for Gate-Level Coupling Delay Calculation.
68-74 BibTeX
Embedded Tutorial
Embedded Tutorial
Topics in Routing
Partial Verification Techniques
Scheduling and Compilation for Embedded Systems
Inductance and Full-Wave Analysis
Placement I
High-Level Design Tools for Analog Circuits
Delay Budgeting and Distribution
Interconnect Analysis
Embedded Tutorial
Embedded Tutorial
Placement II
Analog and RF Simulation
Markovian Analysis and Asynchronous Circuits
Low Power Interconnect Modeling and Optimization
Panel
Static Timing Analysis
- Pinhong Chen, Desmond Kirkpatrick, Kurt Keutzer:
Switching Window Computation for Static Timing Analysis in Presence of Crosstalk Noise.
331-337 BibTeX
- David Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Chanhee Oh, Rajendran Panda:
Slope Propagation in Static Timing Analysis.
338-343 BibTeX
- Pawan Kulshreshtha, Robert Palermo, Mohammad Mortazavi, Cyrus Bamji, Hakan Yalcin:
Transistor-Level Timing Analysis Using Embedded Simulation.
344-348 BibTeX
Embedded Systems Power Management and Validation
Advances in Layout and Synthesis
Embedded Tutorial
Noise and Performance Issues in Routing
Communication Architectures Design and Analysis
Performance Driven Logic Synthesis
New Approaches to At-Speed BIST and Diagnosis
Power Analysis and Optimization
VLIW Exploration and Design Synthesis
Flexibility in Logic Synthesis
Digital and Analog Test Generation
Embedded Tutorial
Embedded Tutorial
Copyright © Sat May 16 23:16:28 2009
by Michael Ley (ley@uni-trier.de)
