38. DAC 2001:
Las Vegas,
Nevada,
USA
Proceedings of the 38th Design Automation Conference, DAC 2001, Las Vegas, NV, USA, June 18-22, 2001.
ACM 2001, ISBN 1-58113-297-2 BibTeX
@proceedings{DBLP:conf/dac/2001,
title = {Proceedings of the 38th Design Automation Conference, DAC 2001,
Las Vegas, NV, USA, June 18-22, 2001},
booktitle = {DAC},
publisher = {ACM},
year = {2001},
isbn = {1-58113-297-2},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Panel
Nanometer Futures
System-Level Configurability:
Bus,
Interface,
and Processor Design
Making Verification More Efficient
- Dong Wang, Pei-Hsin Ho, Jiang Long, James H. Kukula, Yunshan Zhu, Hi-Keung Tony Ma, Robert F. Damiano:
Formal Property Verification by Abstraction Refinement with Formal, Simulation and Hybrid Engines.
35-40
Electronic Edition (link) BibTeX
- Maher N. Mneimneh, Fadi A. Aloul, Christopher T. Weaver, Saugata Chatterjee, Karem A. Sakallah, Todd M. Austin:
Scalable Hybrid Verification of Complex Microprocessors.
41-46
Electronic Edition (link) BibTeX
- Alfred Kölbl, James H. Kukula, Robert F. Damiano:
Symbolic RTL Simulation.
47-52
Electronic Edition (link) BibTeX
SoC and High-Level DFT
Panel
Design for Subwavelength Manufacturability:
Impact on EDA
- Warren Grobman, M. Thompson, R. Wang, C. Yuan, Ruiqi Tian, E. Demircan:
Reticle Enhancement Technology: Implications and Challenges for Physical Design.
73-78
Electronic Edition (link) BibTeX
- Lars Liebmann, Jennifer Lund, Fook-Luen Heng, Ioana Graur:
Enabling Alternating Phase Shifted Mask Designs for a Full Logic Gate Level: Design Rules and Design Rule Checking.
79-84
Electronic Edition (link) BibTeX
- Michael L. Rieger, Jeffrey P. Mayhew, Sridhar Panchapakesan:
Layout Design Methodologies for Sub-Wavelength Manufacturing.
85-88
Electronic Edition (link) BibTeX
- Franklin M. Schellenberg, Olivier Toublan, Luigi Capodieci, Bob Socha:
Adoption of OPC and the Impact on Design and Layout.
89-92
Electronic Edition (link) BibTeX
- Michael Sanie, Michel Côté, Philippe Hurat, Vinod Malhotra:
A Practical Application of Full-Feature Alternating Phase-Shifting Technology for a Phase-Aware Standard-Cell Design Flow.
93-96
Electronic Edition (link) BibTeX
New Ideas in Logic Synthesis
Analog Design and Modeling
Scan-Based Testing
Panel
Configurable Computing:
Reconfiguring the Industry
Interconnect Design Optimization
- Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Paul Villarrubia:
A Practical Methodology for Early Buffer and Wire Resource Allocation.
189-194
Electronic Edition (link) BibTeX
- Elaheh Bozorgzadeh, Ryan Kastner, Majid Sarrafzadeh:
Creating and Exploiting Flexibility in Steiner Trees.
195-198
Electronic Edition (link) BibTeX
- Kevin M. Lepak, Irwan Luwandi, Lei He:
Simultaneous Shield Insertion and Net Ordering under Explicit RLC Noise Constraint.
199-202
Electronic Edition (link) BibTeX
- Hongbing Fan, Jiping Liu, Yu-Liang Wu, Chak-Chung Cheung:
On Optimum Switch Box Designs for 2-D FPGAs.
203-208
Electronic Edition (link) BibTeX
Power Estimation Techniques
Functional Validation Based on Boolean Reasoning (BDD,
SAT)
Verification:
Life Beyond Algorithms
Dissecting an Embedded System:
Lessons from Bluetooth
Algorithmic and Compiler Transformations for High-Level Synthesis
Gate Delay Calculation
Memory,
Bus and Current Testing
Panel
Inductance 101 and Beyond
Memory Optimization Techniques for DSP Processors
Technology Dependant Logic Synthesis
Collaborative and Distributed Design Frameworks
- Juan Antonio Carballo, Stephen W. Director:
Application of Constraint-Based Heuristics in Collaborative Design.
395-400
Electronic Edition (link) BibTeX
- Franc Brglez, Hemang Lavana:
A Universal Client for Distributed Networked Design and Computing.
401-406
Electronic Edition (link) BibTeX
- Darko Kirovski, Milenko Drinic, Miodrag Potkonjak:
Hypermedia-Aided Design.
407-412
Electronic Edition (link) BibTeX
- Tommy Kuhn, Tobias Oppold, Markus Winterholer, Wolfgang Rosenstiel, Mark Edwards, Yaron Kashai:
A Framework for Object Oriented Hardware Specification, Verification, and Synthesis.
413-418
Electronic Edition (link) BibTeX
Panel
Closing the Gap Between ASIC and Custom:
Design Examples
Energy and Flexibility Driven Scheduling
Representation and Optimization for Digital Arithmetic Circuits
Techniques for IP Protection
Visualization and Animation for VLSI Design
Application-Specific Customization for Systems-on-a-Chip
Satisfiability Solvers and Techniques
- Matthew W. Moskewicz, Conor F. Madigan, Ying Zhao, Lintao Zhang, Sharad Malik:
Chaff: Engineering an Efficient SAT Solver.
530-535
Electronic Edition (link) BibTeX
- Aarti Gupta, Anubhav Gupta, Zijiang Yang, Pranav Ashar:
Dynamic Detection and Removal of Inactive Clauses in SAT with Application in Image Computation.
536-541
Electronic Edition (link) BibTeX
- Jesse Whittemore, Joonyoung Kim, Karem A. Sakallah:
SATIRE: A New Incremental Satisfiability Engine.
542-545
Electronic Edition (link) BibTeX
- Emil Gizdarski, Hideo Fujiwara:
A Framework for Low Complexity Static Learning.
546-549
Electronic Edition (link) BibTeX
Power and Interconnect Analysis
Domain Specific Design Methodologies
Panel
Analysis and Implementation for Embedded Systems
Industrial Case Studies in Verification
Integrated High-Level Synthesis Based Solutions
Timing Verification and Simulation
- Murali Kudlugi, Charles Selvidge, Russell Tessier:
Static Scheduling of Multiple Asynchronous Domains For Functional Verification.
647-652
Electronic Edition (link) BibTeX
- Tong Xiao, Malgorzata Marek-Sadowska:
Functional Correlation Analysis in Crosstalk Induced Critical Paths Identification.
653-656
Electronic Edition (link) BibTeX
- Hakan Yalcin, Robert Palermo, Mohammad Mortazavi, Cyrus Bamji, Karem A. Sakallah, John P. Hayes:
An Advanced Timing Characterization Method Using Mode Dependency.
657-660
Electronic Edition (link) BibTeX
- Jing-Jia Liou, Kwang-Ting Cheng, Sandip Kundu, Angela Krstic:
Fast Statistical Timing Analysis By Probabilistic Event Propagation.
661-666
Electronic Edition (link) BibTeX
On-Chip Communication Architectures
- Marco Sgroi, Michael Sheets, Andrew Mihal, Kurt Keutzer, Sharad Malik, Jan M. Rabaey, Alberto L. Sangiovanni-Vincentelli:
Addressing the System-on-a-Chip Interconnect Woes Through Communication-Based Design.
667-672
Electronic Edition (link) BibTeX
- Drew Wingard:
MicroNetwork-Based Integration for SOCs.
673-677
Electronic Edition (link) BibTeX
- Faraydon Karim, Anh Nguyen, Sujit Dey, Ramesh Rao:
On-Chip Communication Architecture for OC-768 Network Processors.
678-683
Electronic Edition (link) BibTeX
- William J. Dally, Brian Towles:
Route Packets, Not Wires: On-Chip Interconnection Networks.
684-689
Electronic Edition (link) BibTeX
Compiler and Architecture Interactions
- Mahmut T. Kandemir, J. Ramanujam, Mary Jane Irwin, Narayanan Vijaykrishnan, Ismail Kadayif, Amisha Parikh:
Dynamic Management of Scratch-Pad Memory Space.
690-695
Electronic Edition (link) BibTeX
- Margarida F. Jacome, Gustavo de Veciana, Satish Pillai:
Clustered VLIW Architectures with Predicated Switching.
696-701
Electronic Edition (link) BibTeX
- Viktor S. Lapinskii, Margarida F. Jacome, Gustavo de Veciana:
High-Quality Operation Binding for Clustered VLIW Datapaths.
702-707
Electronic Edition (link) BibTeX
- Holger Keding, Martin Coors, Olaf Lüthje, Heinrich Meyr:
Fast Bit-True Simulation.
708-713
Electronic Edition (link) BibTeX
Timing with Crosstalk
- Hai Zhou, Narendra V. Shenoy, William Nicholls:
Timing Analysis with Crosstalk as Fixpoints on Complete Lattice.
714-719
Electronic Edition (link) BibTeX
- Supamas Sirichotiyakul, David Blaauw, Chanhee Oh, Rafi Levy, Vladimir Zolotov, Jingyan Zuo:
Driver Modeling and Alignment for Worst-Case Delay Noise.
720-725
Electronic Edition (link) BibTeX
- Ravishankar Arunachalam, Ronald D. Blanton, Lawrence T. Pileggi:
False Coupling Interactions in Static Timing Analysis.
726-731
Electronic Edition (link) BibTeX
- Ki-Wook Kim, Seong-Ook Jung, Prashant Saxena, C. L. Liu, Sung-Mo Kang:
Coupling Delay Optimization by Temporal Decorrelation using Dual Threshold Voltage Technique.
732-737
Electronic Edition (link) BibTeX
Low Power Design:
Systems to Interconnect
Floorplanning Representations and Placement Algorithms
- Jai-Ming Lin, Yao-Wen Chang:
TCG: A Transitive Closure Graph-Based Representation for Non-Slicing Floorplans.
764-769
Electronic Edition (link) BibTeX
- Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu:
Floorplanning with Abutment Constraints and L-Shaped/T-Shaped Blocks based on Corner Block List.
770-775
Electronic Edition (link) BibTeX
- Mehmet Can Yildiz, Patrick H. Madden:
Improved Cut Sequences for Partitioning Based Placement.
776-779
Electronic Edition (link) BibTeX
- Bill Halpin, C. Y. Roger Chen, Naresh Sehgal:
Timing Driven Placement using Physical Net Constraints.
780-783
Electronic Edition (link) BibTeX
- Luca Benini, Luca Macchiarulo, Alberto Macii, Enrico Macii, Massimo Poncino:
From Architecture to Layout: Partitioned Memory Synthesis for Embedded Systems-on-Chip.
784-789
Electronic Edition (link) BibTeX
Panel
Signal Integrity:
Avoidance and Test Techniques
Novel Approaches to Microprocessor Design and Verification
Scheduling Techniques for Power Management
Novel Devices and Yield Optimization
- Rongtian Zhang, Kaushik Roy, Cheng-Kok Koh, David B. Janes:
Exploring SOI Device Structures and Interconnect Architectures for 3-Dimensional Integration.
846-851
Electronic Edition (link) BibTeX
- Seungbae Lee, Gi-Joon Nam, Junseok Chae, Hanseup Kim, Alan J. Drake:
Two-Dimensional Position Detection System with MEMS Accelerometer for MOUSE Applications.
852-857
Electronic Edition (link) BibTeX
- Frank Schenkel, Michael Pronath, Stephan Zizala, Robert Schwencker, Helmut E. Graeb, Kurt Antreich:
Mismatch Analysis and Direct Yield Optimization by Spec-Wise Linearization and Feasibility-Guided Search.
858-863
Electronic Edition (link) BibTeX
Copyright © Sat May 16 23:04:38 2009
by Michael Ley (ley@uni-trier.de)