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ITC 1995: Washington, DC, USA

Proceedings IEEE International Test Conference 1995, Driving Down the Cost of Test, Washington, DC, USA, October 21-25, 1995. IEEE Computer Society 1995, ISBN 0-7803-2992-9 BibTeX
  title     = {Proceedings IEEE International Test Conference 1995, Driving
               Down the Cost of Test, Washington, DC, USA, October 21-25, 1995},
  publisher = {IEEE Computer Society},
  year      = {1995},
  isbn      = {0-7803-2992-9},
  bibsource = {DBLP, http://dblp.uni-trier.de}

Session 1: Plenary

Keynote Address

Invited Address

Session 2: RAM BIST and Intelligent Testing

Session 3: New Test Considerations for Mixed-Signal Devices

Session 4: Quality, I-DDQ, and the DUT Interface

Session 5: Delay Testing

Session 6: Microprocessor Test

Session 7: MCM Test Methods

Session 8: Test SPC and Support Systems

Session 9: Test Generation and Fault Simulation

Session 10 - Panel: Designers are from Venus, Test Engineers are from Mars

Session 11 - Panel: Is High-Level Test Synthesis just DFT?

Session 12 - Panel: Test Challenges of Contract Manufacturing

Session 13 - Panel: Why is Mixed-Signal Testing Such a Mess Anyway?

Session 14 - Panel: Test Quality: Stuck-at Fault, PPM Rejects or?

Session 15: Design for Testability - I

Session 16: IC Test Issues

Session 17: New Test Techniques for Mixed-Signal Devices

Session 18: Microprocessor-Related Topics

Session 19: Design for Testability - II

Session 20: Applications of Test Cost Analysis

Session 21: High-Speed ATE Architectures and Timing

Session 22: Defect Detection and Diagnosis

Session 23: Performance-Driven BIST Insertion

Session 24: IC-Defect Detection: Advancements in Design, Test and Analysis Methods

Session 25: Uniformity and Flexibility: Capatalizing on Boundary-Scan's Assets

Session 26: Test at the Functional Level

Session 27: IC Testing and Diagnosis

Session 28: Topics in Test Techniques

Session 29 - Case Studies: Successful Experiences with MCM Test

Session 30: Synthesis for Testability

Session 31: Software Testing

Session 32 - Case Studies: Test Synthesis

Session 33: Unconventional Test Development

Session 34: Systems and Testing: Practical Applications and Costs

Session 35: BIST Pattern Generation and Compaction

Session 36: Design and Simulations Topics

Session 37: Changing the Test Paradigm: ATE and Board Test Systems

Session 38: IC Current-Test Techniques, Production Results, and Quality Improvement Methods

Session 39 - Panel: Highlights of the MCM Test Workshop

Session 40 - Panel: What New Test Standards Do We Need?

Session 41 - Panel: Bringing Down the Cost of Test... The ATE Way?... The DFT Way?... The Boundary Scan Way?... The I-DDQ Way?... Or What?

Session 42 - Panel: What's so Different about Deep-Submicron Test?

ITC Lecture Series: Unpowered "Opens" Testing

Session T1: Telecom Test: The Future is Here!

Session T2: Design-For-Test Strategies for Novel Telecommunications Test Problems

Session T3: Test Technology and Strategy Challenges Facing Telecom Manufacturing Test

Session T4: Telecom Systems: Are We Getting What We Wanted?

Copyright © Sat May 16 23:26:42 2009 by Michael Ley (ley@uni-trier.de)