Proceedings of the ASPDAC 2002 / VLSI Design 2002, CD-ROM, 7-11 January 2002, Bangalore, India.
IEEE Computer Society 2002, ISBN 0-7695-1299-2 BibTeX
Keynote Talks
Tutorials
- Subir K. Roy, S. Ramesh, Supratik Chakraborty, Tsuneo Nakata, Sreeranga P. Rajan:
Functional Verification of System on Chips-Practices, Issues and Challenges (Tutorial Abstract).
11-13
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- Pieter van der Wolf, W. M. Kruijtzer, Jos T. J. van Eijndhoven:
System-Level Design of Embedded Media Systems (Tutorial Abstract).
14-15
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- Stefan Rusu, Manoj Sachdev, Christer Svensson, B. Nauta:
Trends and Challenges in VLSI Technology Scaling towards 100nm (Tutorial Abstract).
16-17
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- M. V. Atre, P. S. Subramanian, H. Narayanan:
Mathematical Methods in VLSI (Tutorial Abstract).
18-19
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- Vishwani D. Agrawal, Michael L. Bushnell:
Electronic Testing for SOC Designers (Tutorial Abstract).
20
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- Luciano Lavagno, Sujit Dey, Rajesh K. Gupta:
Specification, Modeling and Design Tools for System-on-Chip (Tutorial Abstract).
21-23
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- R. Lal, P. R. Apte, K. N. Bhat, G. Bose, S. Chandra, D. K. Sharma:
MEMS: Technology, Design, CAD and Applications (Tutorial Abstract).
24-25
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- Jordi Cortadella, Alexandre Yakovlev, Jim D. Garside:
Logic Design of Asynchronous Circuits (Tutorial Abstract).
26-
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Low Power I
Interconnects and Technology I
- Joong-Ho Kim, Erdem Matoglu, Jinwoo Choi, Madhavan Swaminathan:
Modeling of Multi-Layered Power Distribution Planes Including Via Effects Using Transmission Matrix Method.
59-64
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- Seung Hoon Choi, Bipul Chandra Paul, Kaushik Roy:
Dynamic Noise Analysis with Capacitive and Inductive Coupling.
65-70
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- Makoto Nagata, Yoshitaka Murasaka, Youichi Nishimori, Takashi Morie, Atsushi Iwata:
Substrate Noise Analysis with Compact Digital Noise Injection and Substrate Models.
71-76
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- Kanak Agarwal, Yu Cao, Takashi Sato, Dennis Sylvester, Chenming Hu:
Efficient Generation of Delay Change Curves for Noise-Aware Static Timing Analysis.
77-
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Synthesis I
Low Power II
Interconnects and Technology II
Synthesis II
Low Power III
Interconnects and Technology III
Synthesis III
- Vishal P. Bhatt, M. Balakrishnan, Anshul Kumar:
Exploring the Number of Register Windows in ASIP Synthesis.
233-238
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- Oliver Schliebusch, Andreas Hoffmann, Achim Nohl, Gunnar Braun, Heinrich Meyr:
Architecture Implementation Using the Machine Description Language LISA.
239-244
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- Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi:
A Framework for Design Space Exploration of Parameterized VLSI Systems.
245-250
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- S. Chakraverty, C. P. Ravikumar, D. Roy Choudhuri:
An Evolutionary Scheme for Cosynthesis of Real-Time Systems.
251-
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Low Power IV
- Kanishka Lahiri, Anand Raghunathan, Sujit Dey, Debashis Panigrahi:
Embedded Tutorial: Battery-Driven System Design: A New Frontier in Low Power Design.
261-267
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- Masanori Muroyama, Tohru Ishihara, Akihiko Hyodo, Hiroto Yasuura:
A Power Minimization Technique for Arithmetic Circuits by Cell Selection.
268-273
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- Yunsi Fei, Niraj K. Jha:
Functional Partitioning for Low Power Distributed Systems of Systems-on-a-Chip.
274-281
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- Tohru Ishihara, Kunihiro Asada:
An Architectural Level Energy Reduction Technique For Deep-Submicron Cache Memories.
282-287
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- Victor Delaluz, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Anand Sivasubramaniam, Ibrahim Kolcu:
Compiler-Directed Array Interleaving for Reducing Energy in Multi-Bank Memories.
288-
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Interconnects and Technology IV
Synthesis IV
Analog Design
Layout I
- Wei Chen, Massoud Pedram, Premal Buch:
Buffered Routing Tree Construction under Buffer Placement Blockages.
381-386
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- Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu:
Stairway Compaction using Corner Block List and Its Applications with Rectilinear Blocks.
387-392
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- Chi-Ming Tsai, Kun-Tien Kuo, Chyi-Hui Hong, Rung-Bin Lin:
An Adaptive Interconnect-Length Driven Placer.
393-398
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- Stelian Alupoaei, Srinivas Katkoori:
Net Clustering Based Macrocell Placement.
399-
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Synthesis and Verification
- Vijay Raghunathan, Anand Raghunathan, Mani B. Srivastava, Milos D. Ercegovac:
High-Level Synthesis with SIMD Units.
407-413
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- J. Ramanujam, Sandeep Deshpande, Jinpyo Hong, Mahmut T. Kandemir:
A Heuristic for Clock Selection in High-Level Synthesis.
414-419
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- Indradeep Ghosh, Krishna Sekar, Vamsi Boppana:
Design for Verification at the Register Transfer Level.
420-425
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- Gabriela Nicolescu, S. Martinez, Lobna Kriaa, Wassim Youssef, Sungjoo Yoo, Benoît Charlot, Ahmed Amine Jerraya:
Application of Multi-Domain and Multi-Language Cosimulation to an Optical MEM Switch Design.
426-
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VLSI Architecture I
- Kavish Seth, S. Srinivasan:
VLSI Implementation of 2-D DWT/IDWT Cores Using 9/7-Tap Filter Banks Based on the Non-Expansive Symmetric Extension Scheme.
435-440
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- Hak-soo Yu, Jacob A. Abraham:
An Efficient 3-Bit -Scan Multiplier without Overlapping Bits, and Its 64x64 Bit Implementation.
441-446
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- Shobha Singh, Shamsi Azmi, Nutan Aarawal, Penaka Phani, Ansuman Rout:
Architecture and Design of a High Performance SRAM for SOC Design.
447-451
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- Jinku Choi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
VLSI Architecture for a Flexible Motion Estimation with Parameters.
452-457
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- Prabhat Mishra, Hiroyuki Tomiyama, Ashok Halambi, Peter Grun, Nikil D. Dutt, Alexandru Nicolau:
Automatic Modeling and Validation of Pipeline Specifications Driven by an Architecture Description Language.
458-
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Layout II
- Yukiko Kubo, Shigetoshi Nakatake, Yoji Kajitani, Masahiro Kawakita:
Explicit Expression and Simultaneous Optimization of Placement and Routing for Analog IC Layouts.
467-472
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- Jingyu Xu, Xianlong Hong, Tong Jing, Yici Cai, Jun Gu:
An Efficient Hierarchical Timing-Driven Steiner Tree Algorithm for Global Routing.
473-478
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- Hiroaki Yoshida, Motohiro Sera, Masao Kubo, Masahiro Fujita:
Simultaneous Circuit Transformation and Routing.
479-483
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- Chunhong Chen:
Probabilistic Analysis of Rectilinear Steiner Trees.
484-488
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- Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh:
Power Supply Noise Aware Floorplanning and Decoupling Capacitance Placement.
489-
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Test and Validation
- Hailong Cui, Sharad C. Seth, Shashank K. Mehta:
A Novel Method to Improve the Test Efficiency of VLSI Tests.
499-504
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- Sandeep Koranne:
On Test Scheduling for Core-Based SOCs.
505-510
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- Yu Huang, Nilanjan Mukherjee, Chien-Chung Tsai, Omer Samman, Yahya Zaidan, Yanping Zhang, Wu-Tung Cheng, Sudhakar M. Reddy:
Constraint Driven Pin Mapping for Concurrent SOC Testing.
511-516
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- Katarzyna Radecka, Zeljko Zilic:
Identifying Redundant Wire Replacements for Synthesis and Verification.
517-523
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- Aarti Gupta, Albert E. Casavant, Pranav Ashar, X. G. Liu, Akira Mukaiyama, Kazutoshi Wakabayashi:
Property-Specific Testbench Generation for Guided Simulation.
524-
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VLSI Architecture II
- Murali Mohan, Rohini Krishnan, Anshul Kumar, M. Balakrishnan:
A New Divide and Conquer Method for Achieving High Speed Division in Hardware.
535-540
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- Tony Han, Sri Parameswaran:
SWASAD: An ASIC Design for High Speed DNA Sequence Matching.
541-546
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- Martin Palkovic, Miguel Miranda, Kristof Denolf, Peter Vos, Francky Catthoor:
Systematic Address and Control Code Transformations for Performance Optimisation of a MPEG-4 Video Decoder.
547-552
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- Debashis Panigrahi, Clark N. Taylor, Sujit Dey:
A Hardware/Software Reconfigurable Architecture for Adaptive Wireless Image Communication.
553-
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Layout III
Test I
Embedded Systems I
- Sornavalli Ramanathan, Rituparna Mandal:
Low Power Solution for Wireless Applications.
615-618
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- J. Ramanujam, Satish Krishnamurthy, Jinpyo Hong, Mahmut T. Kandemir:
Address Code and Arithmetic Optimizations for Embedded Systems.
619-624
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- Yong-Ha Park, Jeonghoon Kook, Hoi-Jun Yoo:
Embedded DRAM (eDRAM) Power-Energy Estimation for System-on-a-Chip (SoC) Applications.
625-630
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- N. E. Crosbie, Mahmut T. Kandemir, Ibrahim Kolcu, J. Ramanujam, Alok N. Choudhary:
Strategies for Improving Data Locality in Embedded Applications.
631-
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Layout IV
Test II
Embedded Systems II
Verification II
Test III
Hot Chips from India
- Karanth Shankaranarayana, Soujanna Sarkar, R. Venkatraman, Shyam S. Jagini, N. Venkatesh, Jagdish C. Rao, H. Udayakumar, M. Sambandam, K. P. Sheshadri, S. Talapatra, Parag Mhatre, Jais Abraham, Rubin A. Parekhji:
Challenges in the Design of a Scalable Data-Acquisition and Processing System-on-Silicon.
781-788
Electronic Edition (link) BibTeX
- Sanjeev Patel:
Development of ASIC Chip-Set for High-End Network Processing Application-A Case Study.
789-794
Electronic Edition (link) BibTeX
- Ranjit Yashwante, Bhalchandra Jahagirdar:
IEEE 1394a_2000 Physical Layer ASIC.
795-800
Electronic Edition (link) BibTeX
- T. Datta, C. S. Muralidharan:
Definition, Design & Development of the IXE2424 Network Switch/Router ASIC.
801-802
Electronic Edition (link) BibTeX
Copyright © Sat May 16 23:46:43 2009
by Michael Ley (ley@uni-trier.de)
