Srinivas Patil

2009
18	EE	Kanupriya Gulati, Suganth Paul, Sunil P. Khatri, Srinivas Patil, Abhijit Jas: FPGA-based hardware acceleration for Boolean satisfiability. ACM Trans. Design Autom. Electr. Syst. 14(2): (2009)
2008
17	EE	Ramtilak Vemu, Abhijit Jas, Jacob A. Abraham, Srinivas Patil, Rajesh Galivanche: A low-cost concurrent error detection technique for processor control logic. DATE 2008: 897-902
2007
16	EE	Abhijit Jas, Srinivas Patil: Analysis of Specified Bit Handling Capability of Combinational Expander Networks. DFT 2007: 252-260
2006
15	EE	Hangkyu Lee, Suriyaprakash Natarajan, Srinivas Patil, Irith Pomeranz: Selecting High-Quality Delay Tests for Manufacturing Test and Debug. DFT 2006: 59-70
14	EE	Suriyaprakash Natarajan, Srinivas Patil, Sreejit Chakravarty: Path Delay Fault Simulation on Large Industrial Designs. VTS 2006: 16-23
2005
13	EE	Kedarnath J. Balakrishnan, Nur A. Touba, Srinivas Patil: Compressing Functional Tests for Microprocessors. Asian Test Symposium 2005: 428-433
1996
12	EE	Rohit Kapur, Srinivas Patil, Thomas J. Snethen, Thomas W. Williams: A weighted random pattern test generation system. IEEE Trans. on CAD of Integrated Circuits and Systems 15(8): 1020-1025 (1996)
1994
11		Rohit Kapur, Srinivas Patil, Thomas J. Snethen, Thomas W. Williams: Design of an Efficient Weighted-Random-Pattern Generation System. ITC 1994: 491-500
10	EE	Jacob Savir, Srinivas Patil: On broad-side delay test. IEEE Trans. VLSI Syst. 2(3): 368-372 (1994)
9	EE	Jacob Savir, Srinivas Patil: Broad-side delay test. IEEE Trans. on CAD of Integrated Circuits and Systems 13(8): 1057-1064 (1994)
1993
8	EE	Jacob Savir, Srinivas Patil: Scan-based transition test. IEEE Trans. on CAD of Integrated Circuits and Systems 12(8): 1232-1241 (1993)
1992
7		Srinivas Patil, Jacob Savir: Skewed-Load Transition Test: Part 2, Coverage. ITC 1992: 714-722
1991
6	EE	Srinivas Patil, Prithviraj Banerjee, Janak H. Patel: Parallel Test Generation for Sequential Circuits on General-Purpose Multiprocessors. DAC 1991: 155-159
5		Sungho Kim, Prithviraj Banerjee, Srinivas Patil: A Layout Driven Design for Testability Technique for MOS VLSI Circuits. ITC 1991: 157-165
4	EE	Srinivas Patil, Prithviraj Banerjee: Performance trade-offs in a parallel test generation/fault simulation environment. IEEE Trans. on CAD of Integrated Circuits and Systems 10(12): 1542-1558 (1991)
1990
3	EE	Srinivas Patil, Prithviraj Banerjee: A parallel branch and bound algorithm for test generation. IEEE Trans. on CAD of Integrated Circuits and Systems 9(3): 313-322 (1990)
1989
2	EE	Srinivas Patil, Prithviraj Banerjee: A Parallel Branch and Bound Algorithm for Test Generation. DAC 1989: 339-343
1		Srinivas Patil, Prithviraj Banerjee: Fault Partitioning Issues in an Integrated Parallel Test Generation/Fault Simulation Environment. ITC 1989: 718-726

Coauthor Index

1	Jacob A. Abraham	[17]
2	Kedarnath J. Balakrishnan	[13]
3	Prithviraj Banerjee (Prith Banerjee)	[1] [2] [3] [4] [5] [6]
4	Sreejit Chakravarty	[14]
5	Rajesh Galivanche	[17]
6	Kanupriya Gulati	[18]
7	Abhijit Jas	[16] [17] [18]
8	Rohit Kapur	[11] [12]
9	Sunil P. Khatri	[18]
10	Sungho Kim	[5]
11	Hangkyu Lee	[15]
12	Suriyaprakash Natarajan	[14] [15]
13	Janak H. Patel	[6]
14	Suganth Paul	[18]
15	Irith Pomeranz	[15]
16	Jacob Savir	[7] [8] [9] [10]
17	Thomas J. Snethen	[11] [12]
18	Nur A. Touba	[13]
19	Ramtilak Vemu	[17]
20	Thomas W. Williams	[11] [12]

Colors in the list of coauthors