10. VLSI Design 1997:
Hyderabad,
India
10th International Conference on VLSI Design (VLSI Design 1997), 4-7 January 1997, Hyderabad, India.
IEEE Computer Society 1997 BibTeX
Tutorials
Session 1:
Monday Keynote Address
Session 2:
Physical Design
Session 3:
Synthesis
- Bernd Becker, Rolf Drechsler:
Decision Diagrams in Synthesis - Algorithms, Applications and Extensions.
46-50
Electronic Edition (link) BibTeX
- Gary William Grewal, Thomas Charles Wilson:
An Enhanced Genetic Solution for Scheduling, Module Allocation, and Binding in VLSI Design.
51-56
Electronic Edition (link) BibTeX
- Madhav Y. Chikodikar, Shridhar Laddha, Ashish Sirasao:
A Technology Mapper for Xilinx FPGAs.
57-61
Electronic Edition (link) BibTeX
- Dong-Hyun Heo, Alice C. Parker, C. P. Ravikumar:
Rapid Synthesis of Multi-Chip Systems.
62-68
Electronic Edition (link) BibTeX
- Gagan Hasteer, Prithviraj Banerjee:
Simulated Annealing Based Parallel State Assignment of Finite State Machines.
69-75
Electronic Edition (link) BibTeX
- Montek Singh, Steven M. Nowick:
Synthesis for Logical Initializability of Synchronous Finite State Machines.
76-81
Electronic Edition (link) BibTeX
Session 4:
Delay Test and Timing
- Seiji Kajihara, Kozo Kinoshita, Irith Pomeranz, Sudhakar M. Reddy:
A Method for Identifying Robust Dependent and Functionally Unsensitizable Paths.
82-87
Electronic Edition (link) BibTeX
- Mandyam-Komar Srinivas, Michael L. Bushnell, Vishwani D. Agrawal:
Flags and Algebra for Sequential Circuit VNR Path Delay Fault Test Generation.
88-94
Electronic Edition (link) BibTeX
- Mukund Sivaraman, Andrzej J. Strojwas:
Primitive Path Delay Fault Identification.
95-100
Electronic Edition (link) BibTeX
- Bernd Becker, Rolf Drechsler, Sudhakar M. Reddy:
(Quasi-) Linear Path Delay Fault Tests for Adders.
101-105
Electronic Edition (link) BibTeX
- Wen-Ben Jone, Yun-Pan Ho, Sunil R. Das:
Delay Fault Coverage Enhancement Using Multiple Test Observation Times.
106-110
Electronic Edition (link) BibTeX
- A. Dharchoudhuri, S. M. Kang:
Analytical Fast Timing Simulation of MOS Circuits Driving RC Interconnects.
111-117
Electronic Edition (link) BibTeX
Session 5:
High-Level Synthesis
Session 6:
HW-SW Codesign
Session 7:
Low-Power Design
Session 8:
Parallel Exhibitor Presentations
Session 9:
Verification
Session 10:
VLSI Systems
- Sunil Nanda:
Media Processors.
244-246
Electronic Edition (link) BibTeX
- Partha Sarathi Bhattacharjee, Sajal K. Das, Debashis Saha, D. Roychowdhury, Parimal Pal Chaudhuri:
A Parallel Architecture for Video Compression.
247-252
Electronic Edition (link) BibTeX
- Giuseppe Ascia, Vincenzo Catania, Giuseppe Ficili:
Design of a VLSI Hardware PET Decoder.
253-256
Electronic Edition (link) BibTeX
- Gab Joong Jeong, Kyoung Hwan Kwon, Moon Key Lee, Seung Han An:
A Scalable Memory System Design.
257-260
Electronic Edition (link) BibTeX
- Milind B. Kamble, Kanad Ghose:
Energy-Efficiency of VLSI Caches: A Comparative Study.
261-267
Electronic Edition (link) BibTeX
- Preeti Ranjan Panda, Nikil D. Dutt:
Behavioral Array Mapping into Multiport Memories Targeting Low Power.
268-273
Electronic Edition (link) BibTeX
Session 11:
Testability Enhancement
- Richard M. Chou, Kewal K. Saluja:
Sequential Circuit Testing: From DFT to SFT.
274-278
Electronic Edition (link) BibTeX
- Shashank K. Mehta, Kent L. Einspahr, Sharad C. Seth:
Synthesis for Testability by Two-Clock Control.
279-283
Electronic Edition (link) BibTeX
- Sudipta Bhawmik, Indradeep Ghosh:
A Practical Method for Selecting Partial Scan Flip-flops for Large Circuits.
284-288
Electronic Edition (link) BibTeX
- Debashis Bhattacharya, S. Freeman, W. Lin:
Optimizing Test Hardware for At-Speed Testing of Datapaths in an Integrated Circuit.
289-296
Electronic Edition (link) BibTeX
- Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar:
Efficient Implementation of Multiple On-Chip Signature Checking.
297-302
Electronic Edition (link) BibTeX
- Debesh Kumar Das, Susanta Chakraborty, Bhargab B. Bhattacharya:
New BIST Techniques for Universal and Robust Testing of CMOS Stuck-Open Faults.
303-309
Electronic Edition (link) BibTeX
Session 12:
Banquet Keynote
Session 13:
Tuesday Keynote Address
Session 14:
Asynchronous Design
- Kimberly D. Emerson:
Asynchronous Design - An Interesting Alternative.
318-321
Electronic Edition (link) BibTeX
- Fu-Chiung Cheng, Stephen H. Unger, Michael Theobald, Wen-Chung Cho:
Delay-Insensitive Carry-Lookahead Adders.
322-328
Electronic Edition (link) BibTeX
- Radhakrishna Nagalla, Graham R. Hellestrand:
A Visual Approach for Asynchronous Circuit Synthesis.
329-335
Electronic Edition (link) BibTeX
- Kamran Eshraghian, Juan A. Montiel-Nelson, Saeid Nooshabadi:
An Asynchronous Morphological Processor for Multi-Media Applications.
336-341
Electronic Edition (link) BibTeX
- K. Nanda, S. K. Desai, S. K. Roy:
A New Methodology for the Design of Asynchronous Digital Circuits.
342-347
Electronic Edition (link) BibTeX
- Raj S. Mitra, Bishnupriya Bhattacharya, Luciano Lavagno:
Asynchronous Implementation of Synchronous Esterel Specifications.
348-355
Electronic Edition (link) BibTeX
Session 15:
Diagnosis
Session 16:
Test and Fault Modeling
Session 17:
Mixed-Signal Design
Session 18:
Architecture
- Ashley Rasquinha, N. Ranganathan:
C3L: A Chip for Connected Component Labeling.
446-450
Electronic Edition (link) BibTeX
- Saeid Nooshabadi, Juan A. Montiel-Nelson, G. S. Visweswaran, D. Nagchoudhuri:
Micropipeline Architecture for Multiplier-less FIR Filters.
451-456
Electronic Edition (link) BibTeX
- Palash Sarkar, Bimal K. Roy, Pabitra Pal Choudhury:
VLSI Implementation of Modulo Multiplication Using Carry Free Addition.
457-460
Electronic Edition (link) BibTeX
- Tales Cleber Pimenta, Luiz Lenarth G. Vermaas, Paulo César Crepaldi, Robson L. Moreno:
The Design of A Digital IC for Thyristor Triggering.
461-464
Electronic Edition (link) BibTeX
- Rana Barua, Samik Sengupta:
Architectures for Arithmetic over GF(2m).
465-469
Electronic Edition (link) BibTeX
Session 9:
ATPG and Fault Simulation
- Irith Pomeranz, Sudhakar M. Reddy:
On the Detection of Reset Faults in Synchronous Sequential Circuits.
470-474
Electronic Edition (link) BibTeX
- Dilip Krishnaswamy, Michael S. Hsiao, Vikram Saxena, Elizabeth M. Rudnick, Janak H. Patel, Prithviraj Banerjee:
Parallel Genetic Algorithms for Simulation-Based Sequential Circuit Test Generation.
475-481
Electronic Edition (link) BibTeX
- C. P. Ravikumar, Vikas Jain, Anurag Dod:
Faster Fault Simulation Through Distributed Computing.
482-487
Electronic Edition (link) BibTeX
- Srimat T. Chakradhar, Vijay Gangaram, Steven G. Rothweiler:
Deriving Signal Constraints to Accelerate Sequential Test Generation.
488-494
Electronic Edition (link) BibTeX
- Elizabeth M. Rudnick, Janak H. Patel:
Overcoming the Serial Logic Simulation Bottleneck in Parallel Fault Simulation.
495-503
Electronic Edition (link) BibTeX
Session 20:
Synthesis and CAD
Session 21:
Design and Implementation
- Ron Lin:
Shift Switching with Domino Logic: Asynchronous VLSI Comparator Schemes.
520-522
Electronic Edition (link) BibTeX
- R. Maheshwari, S. S. S. P. Rao, E. G. Poonach:
FPGA Implementation of Median Filter.
523-524
Electronic Edition (link) BibTeX
- Subhashish Mukherjee, C. Srinivasan, Vivek Pawar, Sumeet Mathur, Kiran Godbole, Eric Soenen:
A 2.5 V 10 bit SAR ADC.
525-526
Electronic Edition (link) BibTeX
- Santanu Chattopadhyay, Parimal Pal Chaudhuri:
Parallel Decoder for Cellular Automata Based Byte Error Correcting Code.
527-528
Electronic Edition (link) BibTeX
- Gosta Pada Biswas, Indranil Sengupta:
A Design Technique of TSC Checker for Borden's Code.
529-530
Electronic Edition (link) BibTeX
- Rajat K. Pal, Sudebkumar Prasant Pal, Ajit Pal:
An Algorithm for Finding a Non-Trivial Lower Bound for Channel Routing.
531-533
Electronic Edition (link) BibTeX
Session 22:
Test and DFT
- Irith Pomeranz, Sudhakar M. Reddy:
On Full Reset as a Design-For-Testability Technique.
534-536
Electronic Edition (link) BibTeX
- Huy Nguyen, Abhijit Chatterjee, Rabindra K. Roy:
Impact of Partial Reset on Fault Independent Testing and BIST.
537-539
Electronic Edition (link) BibTeX
- Raghuram S. Tupuri, Jacob A. Abraham:
A Novel Hierarchical Test Generation Method for Processors.
540-541
Electronic Edition (link) BibTeX
- Charles R. Graham, Elizabeth M. Rudnick, Janak H. Patel:
Dynamic Fault Grouping for PROOFS: A Win for Large Sequential Circuits.
542-544
Electronic Edition (link) BibTeX
- Sankaran M. Menon, Yashwant K. Malaiya, Anura P. Jayasumana:
Input Pattern Classification for Detection of Stuck-ON and Bridging Faults Using I/sub DDQ/ Testing in BiCMOS and CMOS Circuits.
545-546
Electronic Edition (link) BibTeX
- Chunduri Rama Mohan, S. Mitra, Partha Pal Chaudhuri:
On Incorporation of BIST for the Synthesis of Easily and Fully Testable Controllers.
547-563
Electronic Edition (link) BibTeX
Session 23:
Panel Discussion:
The Future of the Indian Information Technology Industry - A CEO's Roundtable
Copyright © Sat May 16 23:46:42 2009
by Michael Ley (ley@uni-trier.de)
