4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India.
IEEE Computer Society 1995, ISBN 0-8186-7129-7 BibTeX
@proceedings{DBLP:conf/ats/1995,
title = {4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore,
India},
booktitle = {Asian Test Symposium},
publisher = {IEEE Computer Society},
year = {1995},
isbn = {0-8186-7129-7},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Systems Test
Analysis Techniques
Diagnosis
Fault Simulation
Mixed-Signal Test
Design for Testability
Education and Research in Testing
Panel
Testability Measures
Delay Test I
ATPG
- Dhruva R. Chakrabarti, Ajai Jain:
An improved hierarchical test generation technique for combinational circuits with repetitive sub-circuits.
237-243
Electronic Edition (link) BibTeX
- Udo Mahlstedt, Jürgen Alt, Ingo Hollenbeck:
Deterministic test generation for non-classical faults on the gate level.
244-251
Electronic Edition (link) BibTeX
- Hiroshi Date, Michinobu Nakao, Kazumi Hatayama:
A parallel sequential test generation system DESCARTES based on real-valued logic simulation.
252-258
Electronic Edition (link) BibTeX
- Tomoo Inoue, Hideo Fujiwara, Hiroyuki Michinishi, Tokumi Yokohira, Takuji Okamoto:
Universal test complexity of field-programmable gate arrays.
259-265
Electronic Edition (link) BibTeX
- Arun Balakrishnan, Srimat T. Chakradhar:
Software transformations for sequential test generation.
266-
Electronic Edition (link) BibTeX
BIST
Self-Checking Circuits
Delay Test II
Technology-Specific Test
Design-Specific Test
Copyright © Sat May 16 22:59:03 2009
by Michael Ley (ley@uni-trier.de)
