6th Asian Test Symposium (ATS '97), 17-18 November 1997, Akita, Japan.
IEEE Computer Society 1997, ISBN 0-8186-8209-4 BibTeX
@proceedings{DBLP:conf/ats/1997,
title = {6th Asian Test Symposium (ATS '97), 17-18 November 1997, Akita,
Japan},
booktitle = {Asian Test Symposium},
publisher = {IEEE Computer Society},
year = {1997},
isbn = {0-8186-8209-4},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Keynote Address
Test Generation I
Design for Testability I
- Silvia Chiusano, Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda:
Guaranteeing Testability in Re-encoding for Low Power.
30-35
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- Marc Perbost, Ludovic Le Lan, Christian Landrault:
Automatic Testability Analysis of Boards and MCMs at Chip Level.
36-41
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- Kwame Osei Boateng, Hiroshi Takahashi, Yuzo Takamatsu:
Design of C-Testable Multipliers Based on the Modified Booth Algorithm.
42-47
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- Shiyi Xu, Peter Waignjo, Percy G. Dias, Bole Shi:
Testability Prediction for Sequential Circuits Using Neural Network.
48-
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Test Generation II
- Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Giovanni Squillero:
A Genetic Algorithm for the Computation of Initialization Sequences for Synchronous Sequential Circuits.
56-61
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- Satoshi Ohtake, Tomoo Inoue, Hideo Fujiwara:
Sequential Test Generation Based on Circuit Pseudo-Transformation.
62-67
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- Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante:
Exploiting Logic Simulation to Improve Simulation-based Sequential ATPG.
68-73
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- Irith Pomeranz, Sudhakar M. Reddy:
TEMPLATES: A Test Generation Procedure for Synchronous Sequential Circuits.
74-
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Fault Tolerance
Case Studies for DFT Techniques in Japanese Industry
- Junji Mori, Ben Mathew, Dave Burns, Yeuk-Hai Mok:
Testability Features of R10000 Microprocessor.
108-111
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- Kazumi Hatayama, Mitsuji Ikeda, Masahiro Takakura, Satoshi Uchiyama, Yoriyuki Sakamoto:
Application of a Design for Delay Testability Approach to High Speed Logic LSIs.
112-115
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- Takaki Yoshida, Reisuke Shimoda, Takashi Mizokawa, Katsuhiro Hirayama:
An effective fault simulation method for core based LSI.
116-121
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- Toshinobu Ono, Kazuo Wakui, Hitoshi Hikima, Yoshiyuki Nakamura, Masaaki Yoshida:
Integrated and Automated Design-for-Testability Implementation for Cell-Based ICs.
122-125
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- Michiaki Emori, Junko Kumagai, Koichi Itaya, Takashi Aikyo, Tomoko Anan, Junichi Niimi:
ATREX : Design for Testability System for Mega Gate LSIs.
126-
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Test Technologies
- Cheng-Wen Wu:
On energy efficiency of VLSI testing.
132-137
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- Marcel Jacomet, Roger Wälti, Lukas Winzenried, Jaime Perez, Martin Gysel:
ProTest: A Low Cost Rapid Prototyping Test System for ASICs and FPGAs.
138-142
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- Vinay Dabholkar, Sreejit Chakravarty:
Computing stress tests for interconnect defects.
143-148
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- Josep Altet, Antonio Rubio, Hideo Tamamoto:
Analysis of the Feasibility of Dynamic Thermal Testing in Digital Circuits.
149-154
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- Zahari M. Darus, Iftekhar Ahmed, Liakot Ali:
A test processor chip implementing multiple seed, multiple polynomial linear feedback shift register.
155-
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Beam Testing of VLSI Circuits in Japan
Mixed-Signal Test
Novel Beam Testing Techniques in Japan
Decision Diagrams and Logic Optimization
FPGA Test
- Hiroyuki Michinishi, Tokumi Yokohira, Takuji Okamoto, Tomoo Inoue, Hideo Fujiwara:
Testing for the programming circuit of LUT-based FPGAs.
242-247
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- Wei-Kang Huang, M. Y. Zhang, Fred J. Meyer, Fabrizio Lombardi:
A XOR-Tree Based Technique for Constant Testability of Configurable FPGAs.
248-253
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- Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian:
Test Pattern and Test Configuration Generation Methodology for the Logic of RAM-Based FPGA.
254-
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Software Test
Diagnosis
Design for Testability II
Delay Test
Built-in Self-Test I
Current Testing
Built-in Self-Test II
Copyright © Sat May 16 22:59:03 2009
by Michael Ley (ley@uni-trier.de)