8. VLSI Design 1995: New Delhi, India

8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India. IEEE Computer Society 1995 BibTeX

1 - Routing I

Srinivasa R. Danda, Sreekrishna Madhwapathy, Naveed A. Sherwani:
Optimal algorithms for planar over-the-cell routing in the presence of obstacles. 3-7
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Andrew Lim, Sartaj K. Sahni, Venkat Thanvantri:
A fast algorithm to test planar topological routability. 8-12
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S. Das, Sanjeev Saxena:
Parallel algorithms for single row routing in narrow streets. 13-18
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2 - Hardware-Software Design

Raj S. Mitra, Mahmood G. Qadir, Anupam Basu:
A consistent labeling approach to hardware software partitioning. 19-24
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Anoop Singhal, Chi-Yuan Lo:
Object oriented data modeling for VLSI/CAD. 25-29
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Raj S. Mitra, Partha S. Roop, Anupam Basu:
Implementation of design functions by available devices: a new algorithm. 30-35
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3 - Sequential Automatic Test Pattern Generation

James Sienicki, Michael L. Bushnell, Prathima Agrawal, Vishwani D. Agrawal:
An asynchronous algorithm for sequential circuit test generation on a network of workstations. 36-41
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Tapan J. Chakraborty, Vishwani D. Agrawal:
Robust testing for stuck-at faults. 42-46
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Mandyam-Komar Srinivas, James Jacob, Vishwani D. Agrawal:
Functional test generation for non-scan sequential circuits. 47-52
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4 - Field Programmable Gate Arrays

Suthikshn Kumar, Kevin E. Forward, M. Palaniswami:
A fast-multiplier generator for FPGAs. 53-56
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Santanu Chattopadhyay, Samir Roy, Parimal Pal Chaudhuri:
Technology mapping on a multi-output logic module built around Cellular Automata Array for a new FPGA architecture. 57-62
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A. Pal, R. K. Gorai, V. V. S. S. Raju:
Synthesis of multiplexer network using ratio parameters and mapping onto FPGAs. 63-68
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Mahesh Mehendale, M. K. Ram Prasad:
AATMA: an algorithm for technology mapping for antifuse-based FPGAs. 69-74
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5 - High-Level Synthesis

Alok Kumar, Anshul Kumar, M. Balakrishnan:
Heuristic search based approach to scheduling, allocation and binding in Data Path Synthesis. 75-80
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Jawahar Jain, Dinos Moundanos, James R. Bitner, Jacob A. Abraham, Donald S. Fussell, Don E. Ross:
Efficient variable ordering and partial representation algorithm. 81-86
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Santonu Sarkar, Anupam Basu, Arun K. Majumdar:
Synchronization of communicating modules and processes in high level synthesis. 87-92
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Alexander Saldanha, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Functional clock schedule optimization. 93-98
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6-Combinational Automatic Test Pattern Generation

Xinghao Chen, Michael L. Bushnell:
Generation of search state equivalence for automatic test pattern generation. 99-103
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Anand Raghunathan, Pranav Ashar, Sharad Malik:
Test generation for cyclic combinational circuits. 104-109
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Sitaran Yadavalli, Irith Pomeranz, Sudhakar M. Reddy:
MUSTC-Testing: Multi-Stage-Combinational Test scheduling at the Register-Transfer Level. 110-115
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S. Venkatraman, Sharad C. Seth, Prathima Agrawal:
Parallel test generation with low communication overhead. 116-120
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7--Logic Synthesis and Retiming

U. K. Bhattacharyya, I. Sen Gupta, S. Shyama Nath, P. Dutta:
PLA based synthesis and testing of hazard free logic. 121-124
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Cristiana Bolchini, Giacomo Buonanno, Donatella Sciuto, Renato Stefanelli:
A new switching-level approach to multiple-output functions synthesis. 125-129
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Sven Simon, Ralf Bucher, Josef A. Nossek:
Retiming of synchronous circuits with variable topology. 130-134
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Srimat T. Chakradhar:
Optimum retiming of large sequential circuits. 135-140
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8-VLSI Arithmetic I

Priyadarsan Patra, Donald S. Fussell:
Fully asynchronous, robust, high-throughput arithmetic structures. 141-145
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Ali Skaf, Alain Guyot:
SAGA: the first general-purpose on-line arithmetic co-processor. 146-149
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S. Krishnakumar, P. Suresh, S. Sadashiva Rao, M. P. Pareek, R. Gupta:
A single chip, pipelined, cascadable, multichannel, signal processor. 150-155
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Luca Penzo, Donatella Sciuto, Cristina Silvano:
VLSI design of systematic odd-weight-column byte error detecting SEC-DED codes. 156-160
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9 - Delay Test

Ananta K. Majhi, James Jacob, Lalit M. Patnaik, Vishwani D. Agrawal:
An efficient automatic test generation system for path delay faults in combinational circuits. 161-165
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Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell:
Statistical methods for delay fault coverage analysis. 166-170
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Steven M. Nowick, Niraj K. Jha, Fu-Chiung Cheng:
Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability. 171-176
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Imtiaz P. Shaik, Michael L. Bushnell:
A graph approach to DFT hardware placement for robust delay fault BIST. 177-182
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10 - Chip Design

P. Jayalakshmi, S. Vidya, S. Krishnakumar, K. Ravisankar, P. Kumar:
A highly testable ASIC for telephone signaling. 183-
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Debabrata Ghosh, Soumitra Kumar Nandy:
Wave pipelined architecture folding: a method to achieve low power and low area. 184-
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Goutam Debnath, K. Debnath, R. Fernando:
The Pentium processor-90/100, microarchitecture and low power circuit design. 185-190
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11 - Tools and Technology Posters

Puneet Sawhney, Haroon Rasheed:
Static RAM generators with automated characterization techniques for a 0.5 micron triple-metal embedded array. 191-
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Varna Puvvada, S. Potla, S. Tamizh Selvam, P. R. Suresh:
A simulation study on the effectiveness of n-guardring/p-guardring on latchup in 0.8 /spl mu/m CMOS technology. 192-
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Nagaraj Subramanyam, K. G. Praveen, Ramesh Ramani, D. Suryanarayana:
CODAC-a characterization system for digital and analog circuits. 193-
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Hameed A. Naseem, Ajay P. Malshe, Rajan A. Beera, M. Shahid Haque, William D. Brown, Len W. Schaper:
CVD-diamond substrates for multi-chip modules (MCMs). 194-
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12 - Panel: India in the VLSI World - High-Tech Innovator or Body Shop?

14 - Routing II

Rajat K. Pal, Sudebkumar Prasant Pal, M. M. Das, Ajit Pal:
Computing area and wire length efficient routes for channels. 196-201
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Rajat K. Pal, A. K. Datta, Sudebkumar Prasant Pal, M. M. Das, Ajit Pal:
A general graph theoretic framework for multi-layer channel routing. 202-207
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Jitendra Khare, Sujoy Mitra, Pranab K. Nag, U. Maly, Rob A. Rutenbar:
Testability-oriented channel routing. 208-213
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15 - Image Compression

Hossein Sahabi, Anup Basu, Mark Fiala:
VLSI implementation of variable resolution image compression. 214-219
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Mario Kovac, N. Ranganathan:
JAGUAR: a high speed VLSI chip for JPEG image compression standard. 220-224
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Jacob Augustine, Wen Feng, James Jacob:
Logic minimization based approach for compressing image data. 225-228
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16 - Analog Circuit Test

Anirudh Devgan, Ronald A. Rohrer:
Efficient simulation of interconnect and mixed analog-digital circuits in ACES. 229-233
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Naveena Nagi, Abhijit Chatterjee, Ashok Balivada, Jacob A. Abraham:
Efficient multisine testing of analog circuits. 234-238
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A. K. B. A'ain, A. H. Bratt, A. P. Dorey:
Exposing floating gate defects in analogue CMOS circuits by power supply voltage control testing technique. 239-242
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17 - Synthesis and Verification

William L. Bradley, Ranga Vemuri:
Transformations for functional verification of synthesized designs. 243-248
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B. M. Subraya, Anshul Kumar, Shashi Kumar:
An HOL based framework for design of correct high level synthesizers. 249-254
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Ramayya Kumar, Thomas Kropf, Klaus Schneider:
Formal synthesis of circuits with a simple handshake protocol. 255-259
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18 - VLSI Technology/CAD

S. Y. Kulkarni, K. D. Patil, K. V. V. Murthy:
Transmission line model parameters for very high speed VLSI interconnects in MCMs using FEM with special elements. 260-263
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D. V. Das:
EM simulation [ICs and MCMs]. 264-267
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G. Hari Rama Krishna, Amit K. Aditya, Nirmal B. Chakrabarti, Swapna Banerjee:
Analysis of temperature dependence of Si-Ge HBT. 268-271
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19 - Testability

C. P. Ravikumar, Hemant Joshi:
HISCOAP: a hierarchical testability analysis tool. 272-277
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S. M. Aziz:
A C-testable modified Booth's array multiplier. 278-282
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Arun Balakrishnan, Srimat T. Chakradhar:
Partial scan design for technology mapped circuits. 283-287
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Elizabeth M. Rudnick, Janak H. Patel:
A genetic approach to test application time reduction for full scan and partial scan circuits. 288-293
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20 - Low-Power/Analog Design

Manjit Borah, Mary Jane Irwin, Robert Michael Owens:
Minimizing power consumption of static CMOS circuits by transistor sizing and input reordering. 294-298
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Vincenzo Catania, Marco Russo:
Analog gates for a VLSI fuzzy processor. 299-304
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S. C. Prasad, Kaushik Roy:
Circuit optimization for minimisation of power consumption under delay constraint. 305-309
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George A. Hadgis, P. R. Mukund:
A novel CMOS monolithic analog multiplier with wide input dynamic range. 310-314
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21 - Array Processor Design

Giuseppe Ascia, Vincenzo Catania:
Design of a VLSI parallel processor for fuzzy computing. 315-320
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Lizy Kurian John, Daniel Brewer, Eugene John:
Design of a highly reconfigurable interconnect for array processors. 321-325
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Meenakshisundaram Gopi, Swami Manohar:
A VLSI architecture for the computation of NURBS patches. 326-331
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V. Visvanathan, S. Ramanathan:
A modular systolic architecture for delayed least mean squares adaptive filtering. 332-337
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22 - Diagnosis and Self-Checking

Sreejit Chakravarty, Yiming Gong:
Voting model based diagnosis of bridging faults in combinational circuits. 338-342
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Santanu Chattopadhyay, Dipanwita Roy Chowdhury, Subarna Bhattacharjee, Parimal Pal Chaudhuri:
Board level fault diagnosis using cellular automata array. 343-348
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Yung-Yuan Chen, Ching-Hwa Cheng, Jwu-E Chen:
An efficient switching network fault diagnosis for reconfigurable VLSI/WSI array processors. 349-354
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B. Ravi Kishore, Rubin A. Parekhji, Sandeep Pagey, Sunil D. Sherlekar, G. Venkatesh:
A new methodology for the design of low-cost fail safe circuits and networks. 355-358
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23 - Floorplanning and Partitioning

Jin-Tai Yan, Pei-Yung Hsiao:
A new fuzzy-clustering-based approach for two-way circuit partitioning. 359-364
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Khushro Shahookar, Pinaki Mazumder:
Genetic multiway partitioning. 365-369
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P. S. Dasgupta, Susmita Sur-Kolay, Bhargab B. Bhattacharya:
VLSI floorplan generation and area optimization using AND-OR graph search. 370-375
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Dinesh Bhatia, James Haralambides:
Resource requirements for field programmable interconnection chips. 376-380
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24 - VLSI Arithmetic II

Luis A. Montalvo, Alain Guyot:
Svoboda-Tung division with no compensation. 381-385
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Alain Guyot, Luis A. Montalvo, A. Houelle, Habib Mehrez, N. Vaucher:
Comparison of the layout synthesis of radix-2 and pseudo-radix-4 dividers. 386-391
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D. V. Poornaiah, P. V. Ananda Mohan:
Design of a 3-bit Booth recoded novel VLSI concurrent multiplier-accumulator architecture. 392-397
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W. Amendola Jr., Hosahalli R. Srinivas, Keshab K. Parhi:
A 16-bit x 16-bit 1.2 /spl mu/ CMOS multiplier with low latency vector merging. 398-402
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25 - Design and Synthesis for Testability

Sunil R. Das, H. T. Ho, Wen-Ben Jone, A. R. Nayak:
An improved output compaction technique for built-in self-test in VLSI circuits. 403-407
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Chunduri Rama Mohan, Partha Pratim Chakrabarti:
Combined optimization of area and testability during state assignment of PLA-based FSM's. 408-413
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Manoj Franklin, Kewal K. Saluja, Kyuchull Kim:
Fast computation of MISR signatures. 414-418
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Jason P. Hurst, Adit D. Singh:
A differential built-in current sensor design for high speed IDDQ testing. 419-423
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