8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 19-21 February 1998, Lafayette, LA, USA.
IEEE Computer Society 1998, ISBN 0-8186-8409-7 BibTeX
@proceedings{DBLP:conf/glvlsi/1998,
title = {8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 19-21 February
1998, Lafayette, LA, USA},
booktitle = {Great Lakes Symposium on VLSI},
publisher = {IEEE Computer Society},
year = {1998},
isbn = {0-8186-8409-7},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Low Power Circuits and Architectures
- Bhanu Kapoor:
Low Power Memory Architectures for Video Applications.
2-6
Electronic Edition (link) BibTeX
- Luca Benini, Giovanni De Micheli, Alberto Macii, Enrico Macii, Massimo Poncino:
Reducing Power Consumption of Dedicated Processors Through Instruction Set Encoding.
8-12
Electronic Edition (link) BibTeX
- A. M. Fahim, Muhammad M. Khellah, Mohamed I. Elmasry:
A Low-Power High-Performance Embedded SRAM Macrocell.
13-17
Electronic Edition (link) BibTeX
- Amr G. Wassal, M. Anwarul Hasan, Mohamed I. Elmasry:
Low-Power Design of Finite Field Multipliers for Wireless Applications.
19-25
Electronic Edition (link) BibTeX
- Dusan Suvakovic, C. Andre T. Salama:
Guidelines for Use of Registers and Multiplexers in Low Power Low Voltage DSP Systems.
26-29
Electronic Edition (link) BibTeX
- Seung-Moon Yoo, Seung-Moon Kang:
A Bootstrapped NMOS Charge Recovery Logic.
30-33
Electronic Edition (link) BibTeX
- Richard F. Hobson:
Power Reducing Techniques for Clocked CMOS PLAs.
34-38
Electronic Edition (link) BibTeX
- Yehea I. Ismail, Eby G. Friedman, José Luis Neves:
Dynamic and Short-Circuit Power of CMOS Gates Driving Lossless Transmission Lines.
39-44
Electronic Edition (link) BibTeX
- Ahmed M. Shams, Magdy A. Bayoumi:
A New Full Adder Cell for Low-Power Applications.
45-
Electronic Edition (link) BibTeX
VLSI Circuits
- Victor Varshavsky:
beta-Driven Threshold Elements.
52-58
Electronic Edition (link) BibTeX
- José G. Delgado-Frias, Jabulani Nyathi:
A VLSI High-Performance Encoder with Priority Lookahead.
59-64
Electronic Edition (link) BibTeX
- Mayukh Bhattacharya, Pinaki Mazumder:
Noise Margins of Threshold Logic Gates containing Resonant Tunneling Diodes.
65-70
Electronic Edition (link) BibTeX
- Azman M. Yusof, Lim Chu Aun, S. M. Rezaul Hasan:
600 MHz Digitally Controlled BiCMOS Oscillator (DCO) for VLSI Signal Processing & Communication Applications.
71-76
Electronic Edition (link) BibTeX
- Tim Bakken, John Choma Jr.:
Stability of a Continuous-Time State Variable Filter with OP-AMP and OTA-C Integrators.
77-82
Electronic Edition (link) BibTeX
- I. Thoidis, Dimitrios Soudris, Ioannis Karafyllidis, Adonios Thanailakis, Thanos Stouraitis:
Multiple-Valued Logic Voltage-Mode Storage Circuits Based On True-Single-Phase Clocked Logic.
83-88
Electronic Edition (link) BibTeX
- João Navarro Jr., Wilhelmus A. M. Van Noije:
CMOS Tapered Buffer Design for Small Width Clock/Data Signal Propagation.
89-94
Electronic Edition (link) BibTeX
- Mohamed Nekili, Yvon Savaria, Guy Bois:
Design of Clock Distribution Networks in Presence of Process Variations.
95-102
Electronic Edition (link) BibTeX
- João Navarro Jr., Wilhelmus A. M. Van Noije:
Design of an 8: 1 MUX at 1.7Gbit/s in 0.8?I`m CMOS Technology.
103-107
Electronic Edition (link) BibTeX
- Pranjal Srivastava, Andrew Pua, Larry Welch:
Issues in the Design of Domino Logic Circuits.
108-112
Electronic Edition (link) BibTeX
- Gianluca Giustolisi, Giovanni Palmisano, Gaetano Palumbo, C. Strano:
A Novel 1.5-V Cmos Mixer.
113-117
Electronic Edition (link) BibTeX
- Can K. Sandalci, Sayfe Kiaei:
Analysis of Adaptive CMOS Down Conversion Mixers.
118-121
Electronic Edition (link) BibTeX
- Hoda S. Abdel-Aty-Zohdy:
Artificial Neural Network Electronic Nose for Volatile Organic Compounds.
122-
Electronic Edition (link) BibTeX
VLSI Architectures
- José G. Delgado-Frias, Richard Diaz:
A VLSI Self-Compacting Buffer for DAMQ Communication Switches.
128-133
Electronic Edition (link) BibTeX
- Adger E. Harvin III, José G. Delgado-Frias:
A Dictionary Machine Emulation on a VLSI Computing Tree System.
134-139
Electronic Edition (link) BibTeX
- Ashutosh Kulkarni, Navin Chander, Soumya Pillai, Lizy Kurian John:
Modeling and Analysis of The Difference-Bit Cache.
140-145
Electronic Edition (link) BibTeX
- Sandeep Agarwal, Fayez El Guibaly:
Modeling of Shift Register-based ATM Switch.
146-151
Electronic Edition (link) BibTeX
- Jen-Chien Tuan, Chein-Wei Jen:
An Architecture of Full-Search Block Matching for Minimum Memory Bandwidth Requirement.
152-156
Electronic Edition (link) BibTeX
- Nien-Tsu Wang, Chen-Wei Shih, Duan Juat Wong-Ho, Nam Ling:
MPEG-2 Video Decoder for DVD.
157-160
Electronic Edition (link) BibTeX
- Eric Senn, Bertrand Zavidovique:
A Self Timed Asynchronous Router for an Heterogeneous Parallel Machine.
161-167
Electronic Edition (link) BibTeX
- Bassem A. Alhalabi, Qutaibah M. Malluhi, Rafic A. Ayoubi:
Non-Refreshing Analog Neural Storage Tailored for On-Chip Learning.
168-
Electronic Edition (link) BibTeX
VLSI Arithmetic
- Yuke Wang, Xiaoyu Song, El Mostapha Aboulhamid:
Residue to Binary Number Converters for (2n-1, 2n, 2n+1).
174-178
Electronic Edition (link) BibTeX
- Inseop Lee, W. Kenneth Jenkins:
The Design of Residue Number System Arithmetic Units for A VLSI Adaptive Equalizer.
179-184
Electronic Edition (link) BibTeX
- Alexander Skavantzos:
An Efficient Residue to Weighted Converter for a New Residue Number System.
185-191
Electronic Edition (link) BibTeX
- Franco Maloberti, Chen Gang:
The Chinese Abacus Method: Can We Use It for Digital Arithmetic?
192-195
Electronic Edition (link) BibTeX
- Gwangwoo Choe, Earl E. Swartzlander Jr.:
Merged Arithmetic for Computing Wavelet Transforms.
196-201
Electronic Edition (link) BibTeX
- Saeid Sadeghi-Emamchaie, Graham A. Jullien, Vassil S. Dimitrov, William C. Miller:
Digital Arithmetic Using Analog Arrays.
202-207
Electronic Edition (link) BibTeX
- James E. Stine, Michael J. Schulte:
A Combined Interval and Floating Point Multiplier.
208-
Electronic Edition (link) BibTeX
Testing
- Irith Pomeranz, Sudhakar M. Reddy:
Test Compaction for Synchronous Sequential Circuits by Test Sequence Recycling.
216-221
Electronic Edition (link) BibTeX
- Rajesh Raina, Robert F. Molyneaux:
Random Self-Test Method - Applications on PowerPC (tm) Microprocessor Caches.
222-229
Electronic Edition (link) BibTeX
- B. Provost, E. Sanchez-Sinencio, Anna Maria Brosa:
A Unified Approach for a Time-Domain Built-In Self-Test Technique and Fault Detection.
230-236
Electronic Edition (link) BibTeX
- F. S. Bietti, Fabrizio Ferrandi, Franco Fummi, Donatella Sciuto:
VHDL Testability Analysis Based on Fault Clustering and Implicit Fault Injection.
237-242
Electronic Edition (link) BibTeX
- Hendrawan Soeleman, Dinesh Somasekhar, Kaushik Roy:
IDD Waveforms Analysis for Testing of Domino and Low Voltage Static CMOS Circuits.
243-248
Electronic Edition (link) BibTeX
- Kaamran Raahemifar, Majid Ahmadi:
A Design-for-Testability Technique for Detecting Delay Faults in Logic Circuits.
249-
Electronic Edition (link) BibTeX
VLSI Communication Circuits and Systems
Algorithms
- Wilsin Gosti, Alberto L. Sangiovanni-Vincentelli, Tiziano Villa, Alexander Saldanha:
An Exact Input Encoding Algorithm for BDDs Representing FSMs.
294-300
Electronic Edition (link) BibTeX
- Sudhakar Bobba, Ibrahim N. Hajj:
Maximum Current Estimation in Programmable Logic Arrays.
301-306
Electronic Edition (link) BibTeX
- Vishwani D. Agrawal, Sharad C. Seth:
Mutually Disjoint Signals and Probability Calculation in Digital Circuits.
307-312
Electronic Edition (link) BibTeX
- Travis E. Doom, Jennifer L. White, Anthony S. Wojcik, Gregory H. Chisholm:
Identifying High-Level Components in Combinational Circuits.
313-318
Electronic Edition (link) BibTeX
- Anthony D. Johnson:
Local Optimality Theory in VLSI Channel Routing: Composite Cyclic Vertical Constraints.
319-324
Electronic Edition (link) BibTeX
- Wolfgang Günther, Rolf Drechsler:
Linear Transformations and Exact Minimization of BDDs.
325-330
Electronic Edition (link) BibTeX
- Luca Benini, Giovanni De Micheli, Antonio Lioy, Enrico Macii, Giuseppe Odasso, Massimo Poncino:
Timed Supersetting and the Synthesis of Telescopic Units.
331-337
Electronic Edition (link) BibTeX
- Sadiq M. Sait, Habib Youssef, Munir M. Zahra:
Tabu Search Based Circuit Optimization.
338-343
Electronic Edition (link) BibTeX
- Dirk Stroobandt, Fadi J. Kurdahi:
On the Characterization of Multi-Point Nets in Electronic Designs.
344-
Electronic Edition (link) BibTeX
Formal Verification
Design Methods
- Mark A. Franklin, Prithvi Prabhu:
Performance Optimization of Self-Timed Circuits.
374-379
Electronic Edition (link) BibTeX
- Ahmad S. Al-Mulhem, Alaaeldin Amin, Habib Youssef:
Stochastic Evolution Algorithm For Technology Mapping.
380-385
Electronic Edition (link) BibTeX
- Kaisheng Wang, Ted Zhihong Yu, Edwin Hsing-Mean Sha:
RCRS: A Framework for Loop Scheduling with Limited Number of Registers.
386-391
Electronic Edition (link) BibTeX
- Herwig Van Marck, Jo Depreitere, Dirk Stroobandt, Jan Van Campenhout:
A Quantitative Study of the Benefits of Area-I/O in FPGAs.
392-399
Electronic Edition (link) BibTeX
- Dale E. Hocevar, Ching-Yu Hung, Dan Pickens, Sundararajan Sriram:
Top-Down Design Using Cycle Based Simulation: an MPEG A/V Decoder Example.
400-
Electronic Edition (link) BibTeX
Low Power
Database for CAD
Copyright © Sat May 16 23:13:52 2009
by Michael Ley (ley@uni-trier.de)
