EURO-DAC 1995:
Brighton,
England,
UK
Proceedings EURO-DAC'95, European Design Automation Conference with EURO-VHDL, Brighton, England, UK, September 18-22, 1995.
IEEE Computer Society 1995, ISBN 0-8186-7156-4 BibTeX
- Ulrich Weinmann, Oliver Bringmann, Wolfgang Rosenstiel:
Device selection for system partitioning.
2-7
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- Markus Schwiegershausen, Peter Pirsch:
A formal approach for the optimization of heterogeneous multiprocessors for complex image processing schemes.
8-13
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- Peter Oehler, Christoph Grimm, Klaus Waldschmidt:
KANDIS - a tool for construction of mixed analog/digital systems.
14-19
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- Peter Conradi:
Information model of a compound graph representation for system and architecture level design.
22-27
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- Cristian A. Giumale, Hilary J. Kahn:
A core information model of VHDL.
28-33
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- Zahir Moosa, Nick Filer, Michael Brown, J. Heaton, J. Pye:
Practical inter-operation of CAD tools using a flexible procedural interface.
34-39
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- D. Wagenblasst, Wolfgang Thronicke:
An approach for classification of integrated circuits by a knowledge conserving library concept.
40-45
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- Luc Rijnders, Zohair Sahraoui, Paul Six, Hugo De Man:
Timing optimization by bit-level arithmetic transformations.
48-53
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- Vigyan Singhal, Carl Pixley, Adnan Aziz, Robert K. Brayton:
Exploiting power-up delay for sequential optimization.
54-59
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- Naveen Ramineni, Malgorzata Chrzanowska-Jeske, Naveen Buddi:
Tree restructuring approach to mapping problem in cellular-architecture FPGAs.
60-65
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- Hans Achatz:
Generating several solutions for the scheduling problem in high-level synthesis.
66-71
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- Tianxiong Xue, Ernest S. Kuh:
Post routing performance optimization via tapered link insertion and wiresizing.
74-79
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- Michael J. Alexander, James P. Cohoon, Joseph L. Ganley, Gabriel Robins:
Performance-oriented placement and routing for field-programmable gate arrays.
80-85
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- Naveen Buddi, Malgorzata Chrzanowska-Jeske, Charles L. Saxe:
Layout synthesis for datapath designs.
86-90
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- Zahir Moosa, Douglas Edwards:
An investigation of iterative routing algorithms.
91-96
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- Srimat T. Chakradhar, Anand Raghunathan:
Bottleneck removal algorithm for dynamic compaction and test cycles reduction.
98-104
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- Irith Pomeranz, Sudhakar M. Reddy:
On generating compact test sequences for synchronous sequential circuits.
105-110
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- Clay Gloster, Franc Brglez:
Partial scan selection for user-specified fault coverage.
111-116
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- Franco Fummi, U. Rovati, Donatella Sciuto:
Testable synthesis of high complex control devices.
117-122
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- Smita Bakshi, Daniel D. Gajski:
A memory selection algorithm for high-performance pipelines.
124-129
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- Andrew A. Duncan, David C. Hendry:
Area efficient DSP datapath synthesis.
130-135
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- Mahsa Vahidi, Alex Orailoglu:
Metric-based transformations for self testable VLSI designs with high test concurrency.
136-141
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- Lars W. Hagen, Dennis J.-H. Huang, Andrew B. Kahng:
On implementation choices for iterative improvement partitioning algorithms.
144-149
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- Ulrike Ober, Manfred Glesner:
Multiway netlist partitioning onto FPGA-based board architecture.
150-155
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- Habib Youssef, Sadiq M. Sait, Khalid J. Al-Farra:
Timing influenced force directed floorplanning.
156-161
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- Thomas Benner, Rolf Ernst, Achim Österling:
Scalable performance scheduling for hardware-software cosynthesis.
164-169
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- Juha-Pekka Soininen, Tuomo Huttunen, Kari Tiensyrjä, Hannu Heusala:
Cosimulation of real-time control systems.
170-175
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- Binh Ngoc Nguyen, Masaharu Imai, Nobuyuki Hikichi:
A hardware/software partitioning algorithm for pipelined instruction set processor.
176-181
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- Gerald Spiegel, Albrecht P. Stroele:
A unified approach to the extraction of realistic multiple bridging and break faults.
184-189
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- Udo Jorczyk, Wilfried Daehn, Oliver Neumann:
Fault modeling of differential ECL.
190-195
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- Alicja Pierzynska, Slawomir Pilarski:
Quality considerations in delay fault testing.
196-201
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- Hannes C. Wittmann, Manfred Henftling:
Path delay ATPG for standard scan design.
202-207
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- Rafael Peset Llopis:
Path sensitization of combinational circuits and its impact on clocking of sequential systems.
210-215
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- Jean Michel Daga, Michel Robert, Daniel Auvergne:
Delay modelling improvement for low voltage applications.
216-221
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- Jerzy Dabrowski:
Functional-level analog macromodeling with piecewise linear signals.
222-227
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- Uwe Gläser, Heinrich Theodor Vierhaus:
FOGBUSTER: an efficient algorithm for sequential test generation.
230-235
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- James Sienicki, Michael L. Bushnell, Prathima Agrawal, Vishwani D. Agrawal:
An adaptive distributed algorithm for sequential circuit test generation.
236-241
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- Zohair Sahraoui, Paul Six, Ivo Bolsens, Hugo De Man:
Search space reduction through clustering in test generation.
242-247
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- Manfred Henftling, Hannes C. Wittmann, Kurt Antreich:
A formal non-heuristic ATPG approach.
248-253
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- Gernot Koch, Udo Kebschull, Wolfgang Rosenstiel:
Debugging of behavioral VHDL specifications by source level emulation.
256-261
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- S. Schmerler, Y. Tanurhan, Klaus D. Müller-Glaser:
A backplane approach for cosimulation in high-level system specification environments.
262-267
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- Ludwig Schwoerer, Matthias Lück, Hartmut Schröder:
Integration of VHDL into a system design environment.
268-273
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- Vladimir B. Dmitriev-Zdorov, Bernhard Klaassen:
An improved relaxation approach for mixed system analysis with several simulation tools.
274-279
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- Theodore Karoubalis, George Alexiou, Nick Kanopoulos:
Optimal synthesis of differential cascode voltage switch (DCVS) logic circuits using ordered binary decision diagrams (OBDDs).
282-287
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- Gianpiero Cabodi, Stefano Quer, Paolo Camurati:
Computing subsets of equivalence classes for large FSMs.
288-293
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- Enrico Macii, Massimo Poncino:
Predicting the functional complexity of combinational circuits by symbolic spectral analysis of Boolean functions.
294-299
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- Alexander N. Soloviev, Alexander L. Stempkovsky:
Model of conceptual design of complex electronic systems.
302-307
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- Ansgar Bredenfeld:
Cooperative concurrency control for design environments.
308-313
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- Jürgen Schubert, Arno Kunzmann, Wolfgang Rosenstiel:
Reduced design time by load distribution with CAD framework methodology information.
314-319
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- Sidharta Mohanty, Philip A. Wilsey:
System modeling, hardware-software codesign, and mixed modeling with hardware description language.
322-327
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- Frank Vahid, Daniel D. Gajski:
Closeness metrics for system-level functional partitioning.
328-333
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- Santhanam Srinivasan, Niraj K. Jha:
Hardware-software co-synthesis of fault-tolerant real-time distributed embedded systems.
334-339
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- Victor V. Toporkov:
Performance-complexity analysis in hardware-software codesign for real-time systems.
340-345
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- Armin Englmaier:
Mesh current method for computing the current distribution in planar conductor surfaces and possible applications in circuit simulation.
348-353
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- E. Leroux, Flavio G. Canavero, G. Vecchi:
Prediction of radiated electromagnetic emissions from PCB traces based on green dyadics.
354-359
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- Konstantin O. Petrosjanc, I. A. Kharitonov, N. I. Rybov, Peter P. Maltcev:
Software system for semiconductor devices, monolith and hybrid ICs thermal analysis.
360-365
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- Thomas Gabler, Sabine März-Rössel:
An approach to guided incremental specification.
368-373
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- Wolfgang Ecker:
Semi-dynamic scheduling of synchronization-mechanisms.
374-379
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- Katsuhiko Shirai, Jin Hiwatashi:
A design system for special purpose processors based on architectures for distributed processing.
380-385
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- Maher Rahmouni, Ahmed Amine Jerraya:
Formulation and evaluation of scheduling techniques for control flow graphs.
386-391
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- Steve Hodgson, Zak Shaar, Andy Smith:
A high performance VHDL simulator for large systems design.
394-399
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- John Willis, Zhiyuan Li, Tsang-Puu Lin:
Use of embedded scheduling to compile VHDL for effective parallel simulation.
400-405
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- Eugen Röhm:
Latest benchmark results of VHDL simulation systems.
406-411
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- Laurent Arditi, Hélène Collavizza:
Towards verifying VHDL descriptions of processors.
414-419
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- Peter T. Breuer, Natividad Martínez Madrid:
A native process algebra for VHDL.
420-426
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- Guido Schumacher, Wolfgang Nebel:
Inheritance concept for signals in object-oriented extensions to VHDL.
428-435
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- Karlheinz Agsteiner, Dieter Monjau, Sören Schulze:
Object-oriented high-level modeling of system components for the generation of VHDL code.
436-441
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- Pierre G. Paulin, Jean Fréhel, Michel Harrand, Elisabeth Berrebi, Clifford Liem, François Naçabal, Jean-Claude Herluison:
High-level synthesis and codesign methods: an application to a videophone codec.
444-451
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- Petru Eles, Krzysztof Kuchcinski, Zebo Peng, Alexa Doboli:
Timing constraint specification and synthesis in behavioral VHDL.
452-457
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- Wolfgang Ecker, Manfred Huber:
VHDL-based communication and synchronization synthesis.
458-462
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- Viktor Preis, Renate Henftling, Markus Schütz, Sabine März-Rössel:
A reuse scenario for the VHDL-based hardware design flow.
464-469
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- Polen Kission, Hong Ding, Ahmed Amine Jerraya:
VHDL based design methodology for hierarchy and component re-use.
470-475
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- Makarand Joshi, Hideaki Kobayashi:
Quantifying design productivity: an effort distribution analysis.
476-481
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- M. Mastretti:
VHDL quality: synthesizability, complexity and efficiency evaluation.
482-487
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- M. M. Kamal Hashmi, Alistair C. Bruce:
Design and use of a system-level specification and verification methodology.
490-495
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- Flávio Rech Wagner:
Design management requirements for hardware description languages.
496-501
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- Serafín Olcoz, Luis Entrena, Luis Berrojo:
An effective system development environment based on VHDL prototyping.
502-507
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- Frank Vahid:
Procedure exlining: a new system-level specification transformation.
508-513
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- Ronald B. Stewart:
LibQA—library quality assurance for VHDL synthesis and simulation.
516-521
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- Vincent Moser, Hans Peter Amann, Pascal Nussbaum, Fausto Pellandini:
Generating VHDL-A—like models using ABSynth.
522-527
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- D. Galán, Carlos J. Jiménez, Angel Barriga Barrios, Santiago Sánchez-Solano:
VHDL package for description of fuzzy logic controllers.
528-533
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- Wolfgang Ecker:
A classification of design steps and their verification.
536-541
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- Ronald Herrmann, Thomas Reielts:
Verification of a production cell using an automatic verification environment for VHDL.
542-547
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- Rainer Schlör, Franz Korf:
Verification of a production cell controller using symbolic timing diagrams.
548-553
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- Markus Schütz:
How to efficiently build VHDL testbenches.
554-559
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- Jan Andersson:
A DSP ASIC design flow based on VHDL and ASIC-emulation.
562-567
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- Joris van den Hurk, Edwin Dilling:
System level design, a VHDL based approach.
568-573
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- Gerhard H. Büttner:
Setting up a retrieval system for design reuse—experiences and acceptance.
575-578
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- Andrea Finotello, Maurizio Paolini:
The VHDL based design of the MIDA MPEG1 audio decoder.
579-584
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- M. Romdhani, P. Chambert, A. Jeffroy, P. de Chazelles, Ahmed Amine Jerraya:
Composing ActivityCharts/StateCharts, SDL and SAO specifications for codesign in avionics.
585-590
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- Paul Vanoostende, Geert van Wauwe:
Issues in low-power design for telecom.
591-593
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- Carol A. Fields:
Creating hierarchy in HDL-based high density FGPA design.
594-599
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- J. Forrest:
ODE: output direct state machine encoding.
600-605
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Copyright © Sat May 16 23:11:13 2009
by Michael Ley (ley@uni-trier.de)
