33. DAC 1996:
Las Vegas,
Nevada,
USA
Proceedings of the 33st Conference on Design Automation,
Las Vegas,
Nevada,
USA,
Las Vegas Convention Center,
June 3-7,
1996. ACM Press,
1996,
ISBN 0-89791-779-0
Executive Forum,
Panel:
The EDA Year in Review:
CEO's,
The Press,
and Users
High Speed Interconnect
Panel:
PCB Synthesis - Is the Technology Ready for High Speed Design?
Power Analysis
Current Directions in High Level Synthesis
Analysis and Synthesis of Asynchronous Circuits
- Eric Verlind, Gjalt G. de Jong, Bill Lin:
Efficient Partial Enumeration for Timing Analysis of Asynchronous Systems.
55-58
Electronic Edition (ACM DL) BibTeX
- Alexei L. Semenov, Alexandre Yakovlev:
Verification of asynchronous circuits using Time Petri Net unfolding.
59-62
Electronic Edition (ACM DL) BibTeX
- Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alexandre Yakovlev:
Methodology and Tools for State Encoding in Asynchronous Circuit Synthesis.
63-66
Electronic Edition (ACM DL) BibTeX
- Prabhakar Kudva, Ganesh Gopalakrishnan, Hans M. Jacobson:
A Technique for Synthesizing Distributed Burst-mode Circuits.
67-70
Electronic Edition (ACM DL) BibTeX
- Michael Theobald, Steven M. Nowick, Tao Wu:
Espresso-HF: A Heuristic Hazard-Free Minimizer for Two-Level Logic.
71-76
Electronic Edition (ACM DL) BibTeX
- Prabhakar Kudva, Ganesh Gopalakrishnan, Hans M. Jacobson, Steven M. Nowick:
Synthesis for Hazard-free Customized CMOS Complex-Gate Networks Under Multiple-Input Changes.
77-82
Electronic Edition (ACM DL) BibTeX
New Frontiers in Partitioning
Trends in Verification
Panel:
Hot New Trends in Verification
Specialized Design Techniques for Speed and Power
Test and Fault Tolerance in High Level Synthesis
Issues in Discrete Simulation
Issues in Design Environments
Panel:
Gearing Up for the Technology Explosion
Tutorial:
The SPICE FET Models:
Pitfalls and Prospects
Combinational Logic Synthesis I
Pattern Generation for Test and Diagnosis
CAD for Analog and Mixed Signal ICs
Panel:
Core-Based Design for System-Level ASICs - Whose Job Is It?
Panel:
A Common Standards Roadmap
Combinational Logic Synthesis II
Design for Testability
Advances in Electrical Simulation
Mixed Signal Design
Panel:
Mixed Signal Designs:
Are There Solutions Today?
Functional Verification of Microprocessors
- Anoosh Hosseini, Dimitrios Mavroidis, Pavlos Konas:
Code Generation and Analysis for the Functional Verification of Microprocessors.
305-310
Electronic Edition (ACM DL) BibTeX
- Val Popescu, Bill McNamara:
Innovative Verification Strategy Reduces Design Cycle Time for High-End Sparc Processor.
311-314
Electronic Edition (ACM DL) BibTeX
- Gopi Ganapathy, Ram Narayan, Glenn Jorden, Denzil Fernandez, Ming Wang, Jim Nishimura:
Hardware Emulation for Functional Verification of K5.
315-318
Electronic Edition (ACM DL) BibTeX
- James Monaco, David Holloway, Rajesh Raina:
Functional Verification Methodology for the PowerPC 604 Microprocessor.
319-324
Electronic Edition (ACM DL) BibTeX
- Michael Kantrowitz, Lisa M. Noack:
I'm Done Simulating: Now What? Verification Coverage Analysis and Correctness Checking of the DECchip 21164 Alpha Microprocessor.
325-330
Electronic Edition (ACM DL) BibTeX
High Level Power Optimization
3-D Parasitic Extraction
- Byron Krauter, Yu Xia, E. Aykut Dengi, Lawrence T. Pileggi:
A Sparse Image Method for BEM Capacitance Extraction.
357-362
Electronic Edition (ACM DL) BibTeX
- Narayan R. Aluru, V. B. Nadkarni, James White:
A Parallel Precorrected FFT Based Capacitance Extraction Program for Signal Integrity Analysis.
363-366
Electronic Edition (ACM DL) BibTeX
- Johannes Tausch, Jacob K. White:
Multipole Accelerated Capacitance Calculation for Structures with Multiple Dielectrics with high Permittivity Ratios.
367-370
Electronic Edition (ACM DL) BibTeX
- Weikai Sun, Wayne Wei-Ming Dai, Wei Hong II:
Fast Parameters Extraction of General Three-Dimension Interconnects Using Geometry Independent Measured Equation of Invariance.
371-376
Electronic Edition (ACM DL) BibTeX
- Joel R. Philips, Eli Chiprout, David D. Ling:
Efficient Full-Wave Electromagnetic Analysis via Model-Order Reduction of Fast Integral Transforms.
377-382
Electronic Edition (ACM DL) BibTeX
Routing Optimization for Performance
- Joe G. Xi, Wayne Wei-Ming Dai:
Useful-Skew Clock Routing With Gate Sizing for Low Power Design.
383-388
Electronic Edition (ACM DL) BibTeX
- Madhav P. Desai, Radenko Cvijetic, James Jensen:
Sizing of Clock Distribution Networks for High Performance CPU Chips.
389-394
Electronic Edition (ACM DL) BibTeX
- John Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin, Chin-Yen Ho:
New Performance Driven Routing Techniques With Explicit Area/Delay Tradeoff and Simultaneous Wire Sizing.
395-400
Electronic Edition (ACM DL) BibTeX
- Jaewon Oh, Iksoo Pyo, Massoud Pedram:
Constructing Lower and Upper Bounded Delay Routing Trees Using Linear Programming.
401-404
Electronic Edition (ACM DL) BibTeX
- Chung-Ping Chen, Yao-Wen Chang, D. F. Wong:
Fast Performance-Driven Optimization for Buffered Clock Trees Based on Lagrangian Relaxation.
405-408
Electronic Edition (ACM DL) BibTeX
Tutorial:
How to Write Awk and Perl Scripts to Enable Your EDA Tools to Work Together
Functional Verification Techniques
- K. D. Jones, J. P. Privitera:
The Automatic Generation of Functional Test Vectors for Rambus Designs.
415-420
Electronic Edition (ACM DL) BibTeX
- Françoise Casaubieilh, Anthony McIsaac, Mike Benjamin, Mike Bartley, François Pogodalla, Frédéric Rocheteau, Mohamed Belhadj, Jeremy Eggleton, Gérard Mas, Geoff Barrett, Christian Berthet:
Functional Verification Methodology of Chameleon Processor.
421-426
Electronic Edition (ACM DL) BibTeX
- Stephen Dean Brown, Naraig Manjikian, Zvonko G. Vranesic, S. Caranci, A. Grbic, R. Grindley, M. Gusat, K. Loveless, Zeljko Zilic, Sinisa Srbljic:
Experience in Designing a Large-scale Multiprocessor using Field-Programmable Devices and Advanced CAD Tools.
427-432
Electronic Edition (ACM DL) BibTeX
Power Estimation
Optimization of Sequential Circuits
- Sunil P. Khatri, Amit Narayan, Sriram C. Krishnan, Kenneth L. McMillan, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Engineering Change in a Non-Deterministic FSM Setting.
451-456
Electronic Edition (ACM DL) BibTeX
- Mahesh A. Iyer, David E. Long, Miron Abramovici:
Identifying Sequential Redundancies Without Search.
457-462
Electronic Edition (ACM DL) BibTeX
- Hiroyuki Higuchi, Yusuke Matsunaga:
A Fast State Reduction Algorithm for Incompletely Specified Finite State Machines.
463-466
Electronic Edition (ACM DL) BibTeX
- Fabrizio Ferrandi, Franco Fummi, Enrico Macii, Massimo Poncino, Donatella Sciuto:
Symbolic Optimization of FSM Networks Based on Sequential ATPG Techniques.
467-470
Electronic Edition (ACM DL) BibTeX
Topics in Physical Design
Consumer Product Design
Tutorial:
Issues and Answers in CAD Tool Interoperability
Hardware-Software Co-Design
Timing and Power
Verification of Sequential Systems
Panel:
Electronic Connectivity + EDA Data = Electronic Commerce
Experience with High Level Synthesis
- Elisabeth Berrebi, Polen Kission, Serge Vernalde, S. De Troch, Jean-Claude Herluison, Jean Fréhel, Ahmed Amine Jerraya, Ivo Bolsens:
Combined Control Flow Dominated and Data Flow Dominated High-Level Synthesis.
573-578
Electronic Edition (ACM DL) BibTeX
- J. Huisken, F. Welten:
FADIC: Architectural Synthesis applied in IC Design.
579-584
Electronic Edition (ACM DL) BibTeX
- Mike Tien-Chien Lee, Yu-Chin Hsu, Ben Chen, Masahiro Fujita:
Domain-Specific High-Level Modeling and Synthesis for ATM Switch Design Using VHDL.
585-590
Electronic Edition (ACM DL) BibTeX
Analysis and Compilation for Embedded Software
Timing Modeling and Optimization
Decision Diagrams and Their Application
Formal Methods
Applications for Hardware/Software Codesign
Power Estimation and Retiming
Technology Dependent Performance Driven Synthesis
Layout Analysis and Optimization
Panel:
System Synthesis:
Can we Meet the Challenges to Come?
Hardware Description Language Techniques
Power Minimization in IC Design
Advanced Test Solutions
Technology Optimization for Cells and Systems
Copyright © Sat May 16 23:04:37 2009
by Michael Ley (ley@uni-trier.de)
