VTS 1998:
Princeton,
NJ,
USA
16th IEEE VLSI Test Symposium (VTS '98), 28 April - 1 May 1998, Princeton, NJ, USA.
IEEE Computer Society 1998, ISBN 0-8186-8436-4 BibTeX
Core and System on Chip Test
- Stephen V. Kosonocky, Arthur A. Bright, Kevin W. Warren, Ruud A. Haring, Steve Klepner, Sameh W. Asaad, S. Basavaiah, Bob Havreluk, David F. Heidel, Michael Immediato, Keith A. Jenkins, Rajiv V. Joshi, Ben Parker, T. V. Rajeevakumar, Kevin G. Stawiasz:
Designing a Testable System on a Chip.
2-7
Electronic Edition (link) BibTeX
- Debashis Bhattacharya:
Hierarchical Test Access Architecture for Embedded Cores in an Integrated Circuit.
8-14
Electronic Edition (link) BibTeX
- Mehrdad Nourani, Christos A. Papachristou:
Parallelism in Structural Fault Testing of Embedded Cores.
15-21
Electronic Edition (link) BibTeX
Testing Deep Submicron Circuits
Diagnosis and Validation
BIST 1
Scan & Boundary Scan
IDDQ and VLV Test
Analog Test
Sequential Test and Redundancy Removal
Embedded Tutorial 1
Delay Fault Test
BIST 2
Testing High-Speed Circuits
- David F. Heidel, Sang H. Dhong, H. Peter Hofstee, Michael Immediato, Kevin J. Nowka, Joel Silberman, Kevin G. Stawiasz:
High-Speed Serializing/De-Serializing Design-For-Test Method for Evaluating a 1 GHz Microprocessor.
234-238
Electronic Edition (link) BibTeX
- Iboun Taimiya Sylla, Mustapha Slamani, Bozena Kaminska, Fartoumi M. Hossein, Patrick Vincent:
Impedance Mismatch and Lumped Capacitance Effects in High Frequency Testing.
239-244
Electronic Edition (link) BibTeX
- Ralph Mason, Shing Ma:
Mixed Signal DFT at GHz Frequencies.
245-253
Electronic Edition (link) BibTeX
Validation/Verification
Defect Level Test
Concurrent Checking & Fault Tolerance
Panel 1
Panel and Embedded Tutorial 2
Embedded Tutorial 3
Scan Techniques
On-Line Testing
Analog/Mixed Signal Test and DFT
Memory Test
BIST 3
New ATPG Techniques
Panel 3
Embedded Tutorial 4
Panel 4
Copyright © Sat May 16 23:47:02 2009
by Michael Ley (ley@uni-trier.de)
