11. ACM Great Lakes Symposium on VLSI 2001: West Lafayette, Indiana, USA

@proceedings{DBLP:conf/glvlsi/2001,
  editor    = {Kaushik Roy and
               Sung-Mo Kang and
               Cheng-Kok Koh},
  title     = {Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001,
               West Lafayette, Indiana, USA, 2001},
  booktitle = {ACM Great Lakes Symposium on VLSI},
  publisher = {ACM},
  year      = {2001},
  isbn      = {1-58113-351-0},
  bibsource = {DBLP, http://dblp.uni-trier.de}
}

• Leila Barakatain, Sofiène Tahar, Jean Lamarche, Jean-Marc Gendreau:
  Practical approaches to the verification of a telecom megacell using FormalCheck. 1-6
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• Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos:
  A novel reseeding technique for accumulator-based test pattern generation. 7-12
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• Irith Pomeranz, Sudhakar M. Reddy:
  ITEM: an iterative improvement test generation procedure for synchronous sequential circuits. 13-18
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• Florin Balasa, Werner Geurts, Francky Catthoor, Hugo De Man:
  Solving large scale assignment problems in high-level synthesis by approximative quadratic programming. 19-24
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• Abhishek Ranjan, Ankur Srivastava, V. Karnam, Majid Sarrafzadeh:
  Layout aware retiming. 25-30
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• Zhong Wang, Edwin Hsing-Mean Sha, Yuke Wang:
  Optimal partitioning and balanced scheduling with the maximal overlap of data footprints. 31-36
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• Rajiv V. Joshi, Wei Hwang, Ching-Te Chuang:
  SOI for asynchronous dynamic circuits. 37-42
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• Ram Krishnamurthy, Mark Anders, K. Soumyanath, Shekhar Borkar:
  Leakage control and tolerance challenges for sub-0.1µm microprocessor circuits. 43-44
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• Khurram Muhammad, Robert B. Staszewski, Poras T. Balsara:
  Challenges in integrated CMOS transceivers for short distance wireless. 45-50
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• Nak-Woong Eum, Taewhan Kim, Chong-Min Kyung:
  An accurate evaluation of routing density for symmetrical FPGAs. 51-55
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• Mehmet Can Yildiz, Patrick H. Madden:
  Preferred direction Steiner trees. 56-61
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• Hung-Ming Chen, D. F. Wong, Wai-Kei Mak, Hannah Honghua Yang:
  Faster and more accurate wiring evaluation in interconnect-centric floorplanning. 62-67
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• Mehmet Can Yildiz, Patrick H. Madden:
  Global objectives for standard cell placement. 68-72
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• Alper Buyuktosunoglu, David H. Albonesi, Stanley Schuster, David Brooks, Pradip Bose, Peter W. Cook:
  A circuit level implementation of an adaptive issue queue for power-aware microprocessors. 73-78
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• Bipul Das, Swapna Banerjee:
  A CORDIC based array architecture for complex discrete wavelet transform. 79-84
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• José G. Delgado-Frias, Girish B. Ratanpal:
  A VLSI wrapped wave front arbiter for crossbar switches. 85-88
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• Edward Ahn, Seung-Moon Yoo, Sung-Mo Kang:
  Effective algorithms for cache-level compression. 89-92
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• Seung-Moon Yoo, Seong-Ook Jung, Sung-Mo Kang:
  2-level LFSR scheme with asynchronous test pattern transfer for low cost and high efficiency build-in-self-test. 93-96
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• Malay K. Ganai, Adnan Aziz:
  Rarity based guided state space search. 97-102
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• Chih-Wei Jim Chang, Malgorzata Marek-Sadowska:
  Who are the alternative wires in your neighborhood? (alternative wires identification without search). 103-108
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• Yu-Min Lee, Charlie Chung-Ping Chen:
  Hierarchical model order reduction for signal-integrity interconnect synthesis. 109-114
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• Min Xu, Lei He:
  An efficient model for frequency-dependent on-chip inductance. 115-120
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• Lijun Gao, Keshab K. Parhi:
  Models for power consumption and power grid noise due to datapath transition activity. 121-126
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• Deepak Srivastava:
  Electronic devices, structures and transport in carbon based materials: molecular electronics and quantum computing. 127
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• Mark C. Hersam:
  Single molecule electronics. 128
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• John P. Denton, Sang Woo Pae, Gerold W. Neudeck:
  Vertical integration of submicron MOSFETs in two separate layers of SOI islands formed by silicon epitaxial lateral overgrowth. 129-132
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• Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang:
  Transistor sizing for reliable domino logic design in dual threshold voltage technologies. 133-138
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• José M. Quintana, Maria J. Avedillo, Raúl Jiménez, Esther Rodríguez-Villegas:
  Practical low-cost CPL implementations threshold logic functions. 139-144
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• A. P. Preethy, Damu Radhakrishnan, Amos Omondi:
  A high performance RNS multiply-accumulate unit. 145-148
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• Ohsang Kwon, Earl E. Swartzlander Jr., Kevin J. Nowka:
  A fast hybrid carry-lookahead/carry-select adder design. 149-152
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