VTS 2003:
Napa Valley,
CA,
USA
21st IEEE VLSI Test Symposium (VTS 2003), 27 April - 1 May 2003, Napa Valley, CA, USA.
IEEE Computer Society 2003, ISBN 0-7695-1924-5 BibTeX
Plenary Session
New Directions in Scan Test
Outlier Identification & Current Based Test
Advances in Built-In Self-Test - I
Analog and Mixed-Signal Test - I
Test Compaction
Testing Buses and On-Chip Interconnect
Test Challenges in Nanometer Technologies
Advanced Test Generation and Fault Simulation Techniques
Analog and Mixed-Signal Test - 2
Test Data Compression
Memory Testing
Power Consumption and Test
Testing Core-Based SoCs
Panel
System-Level Test Issues
Diagnosis Techniques
- Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, Jing-Jia Liou:
Diagnosis of Delay Defects Using Statistical Timing Models.
339-344
Electronic Edition (link) BibTeX
- Ananta K. Majhi, Guido Gronthoud, Camelia Hora, Maurice Lousberg, Pop Valer, Stefan Eichenberger:
Improving Diagnostic Resolution of Delay Faults using Path Delay Fault Model.
345-350
Electronic Edition (link) BibTeX
- Xiaoming Yu, Enamul Amyeen, Srikanth Venkataraman, Ruifeng Guo, Irith Pomeranz:
Concurrent Execution of Diagnostic Fault Simulation and Equivalence Identification During Diagnostic Test Generation.
351-358
Electronic Edition (link) BibTeX
Advances in Built-In Self-Test - 2
Test in the Presence of Bridging Faults
- Zhuo Li, Xiang Lu, Wangqi Qiu, Weiping Shi, D. M. H. Walker:
A Circuit Level Fault Model for Resistive Opens and Bridges.
379-384
Electronic Edition (link) BibTeX
- Shahdad Irajpour, Shahin Nazarian, Lei Wang, Sandeep K. Gupta, Melvin A. Breuer:
Analyzing Crosstalk in the Presence of Weak Bridge Defects.
385-392
Electronic Edition (link) BibTeX
- Manan Syal, Michael S. Hsiao, Kiran B. Doreswamy, Sreejit Chakravarty:
Efficient Implication - Based Untestable Bridge Fault Identifier.
393-402
Electronic Edition (link) BibTeX
Emerging Circuit Technologies:
Test Challenges
Copyright © Sat May 16 23:47:01 2009
by Michael Ley (ley@uni-trier.de)
