ICCD 2004:
San Jose,
CA,
USA
22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 11-13 October 2004, San Jose, CA, USA, Proceedings.
IEEE Computer Society 2004, ISBN 0-7695-2231-9 BibTeX
Session 1
Session 1.1 High-Speed and Energy-Efficient Circuit Design
- Mohammad J. Akhbarizadeh, Mehrdad Nourani, Deepak S. Vijayasarathi, Poras T. Balsara:
PCAM: A Ternary CAM Optimized for Longest Prefix Matching Tasks.
6-11
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- Srinivasa R. Sridhara, Arshad Ahmed, Naresh R. Shanbhag:
Area and Energy-Efficient Crosstalk Avoidance Codes for On-Chip Buses.
12-17
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- Justin Hensley, Anselmo Lastra, Montek Singh:
An Area- and Energy-Efficient Asynchronous Booth Multiplier for Mobile Devices.
18-25
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- Robert D. Kenney, Michael J. Schulte, Mark A. Erle:
A High-Frequency Decimal Multiplier.
26-29
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- Magnus Själander, Henrik Eriksson, Per Larsson-Edefors:
An Efficient Twin-Precision Multiplier.
30-33
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Session 1.2 Energy-Efficient Processor Microarchitecture (1)
Session 1.3 Scan Design and Test
Session 2
Session 2.1 Routing and Floorplanning
Session 2.2 Formal Verification Embedded Tutorial
Session 2.3 Signal Integrity and Leakage
Session 3
Session 3.1 Special Session on High-Performance On-Chip Communication.
Session 3.2 Test Generation and Characterization
- Jinkyu Lee, Nur A. Touba:
Low Power Test Data Compression Based on LFSR Reseeding.
180-185
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- Jui-Jer Huang, Jiun-Lang Huang:
An Infrastructure IP for On-Chip Clock Jitter Measurement.
186-191
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- Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski:
Diagnosis of Hold Time Defects.
192-199
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- Baris Arslan, Ozgur Sinanoglu, Alex Orailoglu:
Extending the Applicability of Parallel-Serial Scan Designs.
200-203
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- Roy Emek, Itai Jaeger, Yoav Katz, Yehuda Naveh:
Quality Improvement Methods for System-Level Stimuli Generation.
204-206
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Session 3.3 Physically-Aware Design Tools
Session 4
Session 4.1 Energy-Efficient Processor Microarchitecture (2)
Session 4.2 Power and Timing Optimization
Session 4.3 Novel Processor Design
Session 5
Session 5.1 Emerging Technologies Special Session
Session 5.2 Cache Memory Design
Session 6
Session 6.1 Layout-Driven Circuit Optimization
- Yajun Ran, Malgorzata Marek-Sadowska:
The Magic of a Via-Configurable Regular Fabric.
338-343
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- Yi Zou, Yici Cai, Qiang Zhou, Xianlong Hong, Sheldon X.-D. Tan:
A Fast Delay Analysis Algorithm for The Hybrid Structured Clock Network.
344-349
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- Ingmar Neumann, Dominik Stoffel, Kolja Sulimma, Michel R. C. M. Berkelaar, Wolfgang Kunz:
Layout Driven Optimization of Datapath Circuits using Arithmetic Reasoning.
350-353
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- Dongku Kang, Hunsoo Choo, Kaushik Roy:
Floorplan-Aware Low-Complexity Digital Filter Synthesis for Low-Power & High-Speed.
354-357
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Session 6.2 Instruction-Level Parallelism (1)
Session 6.3 Power Estimation and Minimization
Session 7
Session 7.1 Formal Verification Techniques
Session 7.2 Networks on Chips
Session 7.3 Novel Processor Architecture
- Liang Han, Jie Chen, Chaoxian Zhou, Ying Li, Xin Zhang, Zhibi Liu, Xiaoyun Wei, Baofeng Li:
An Embedded Reconfigurable SIMD DSP with Capability of Dimension-Controllable Vector Processing.
446-451
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- A. Murat Fiskiran, Ruby B. Lee:
Runtime Execution Monitoring (REM) to Detect and Prevent Malicious Code Execution.
452-457
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- Jiangjiang Liu, Krishnan Sundaresan, Nihar R. Mahapatra:
Dynamic Address Compression Schemes: A Performance, Energy, and Cost Study.
458-463
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Session 8
Session 8.1 Instruction-Level Parallelism (2)
Session 8.2 Topics in Synthesis and Co-Simulation
- Hu Huang, Joseph B. Bernstein, Martin Peckerar, Ji Luo:
Combined Channel Segmentation and Buffer Insertion for Routability and Performance Improvement of Field.
490-495
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- Franco Fummi, Stefano Martini, Marco Monguzzi, Giovanni Perbellini, Massimo Poncino:
Software/Network Co-Simulation of Heterogeneous Industrial Networks Architectures.
496-501
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- Jinwen Xi, Peixin Zhong:
Hardware/Software Co-Modeling of SAT Solver Based on Distributed Computing Elements using SystemC.
502-504
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- Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Christos P. Sotiriou:
Coping with The Variability of Combinational Logic Delays.
505-508
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Session 8.3 Low-Power Architecture
Session 9
Session 9.1 Test Generation
Session 9.2 Network Routing
Session 9.3 Placement and Floorplanning
Copyright © Sat May 16 23:16:37 2009
by Michael Ley (ley@uni-trier.de)
